With this change, Add option to support
prefixing crash dump files with timestamp prefix
Change-Id: I30343e6d7dc58376264dd34a4a3cd25bb34e65c6
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This change will read calibration data from the 0:ART partition and
apply it to the appropriate registers.
Change-Id: Ic9360c0fce229c1d1867ee897b811abc56d2b1c7
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
When xbl logs are disabled no logs came in uart console
due to gcc_blsp1_ahb_clk in disabled state.
This patch enables gcc_blsp1_ahb_clk in u-boot to avoid this issue.
Change-Id: I161b003096544e54d3d230027c2665e8fa3d0f5e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The main loop contains an eth init sequence,
to achieve this, remove the eth init sequence
from bootipq.avoid reinitialization.
Support for the IPQ5332 SoC has been added.
Change-Id: I18406dc90ba6845ce367215a55794ba5e400d5d3
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change creates Al02-c9 dts file to help with pci enumeration
Change-Id: I9a743de8ebbdc3f4ee43c14204ab1244e8945a12
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This patch removes the flash detection code in fdtfixup as it will be
taken care based on the boot flash type
Reference Commit:
425d52cd85 (avoid multiple machid for nand/mmc boot)
Change-Id: I51739ae539a568a1480a26fb9143be01306ce39a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch enables i2c usb and pci in AP-MI01.2 and AP-MI01.4.
Change-Id: I4f09485fcbad4247aa75676cb72dc4345405fdfc
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch enables support for USB 2.0 in AP-MI01.2
Change-Id: I4f848a403f3aae45a9f1cfa136781fbc7a37c35a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The pcie AUX clock source changed to XO as per
GCC frequency plan
Change-Id: If032831d3a9523ec214a62cbed2950ee5839920e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
added boot type based nand or emmc flash selection.
So machid based flash selection becomes obsolete.
Change-Id: I96fa43d31d23397fa249e02f62b905d6e4e67770
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
For 192MHz:
GCC_SDCC1_APPS_CFG_RCGR(0x1833008) set to 0x220b
GCC_SDCC1_APPS_M(0x183300c) set to 0x0
GCC_SDCC1_APPS_N(0X1833010) set to 0x0
GCC_SDCC1_APPS_D(0x1833014) set to 0x0
Change-Id: I2715b4428e4390f0b9b0b159e984a718d6c791a3
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
This patch adds support to enable flash using machid
Change-Id: I745a941d4219dc4cd29be96876710e15185ecb8f
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This changes includes update the Speed clock,
common clock update and dts nodes.
Change-Id: I673e8ccf191048fef966a8f6cd84858e1a3b824f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Only one SFP port can be enabled at time with
either SGMII or SGMII PLUS mode.
Mode shall be specified from dts for 1G or 2.5G
support respectively. Add below change to enable
SFP as this change is not mainlined.
gmac_cfg {
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
- phy_address = <0x1c>;
- napa_gpio = <39>;
/*
* 6 - SGMII_PLUS (2.5G),
* 8 - SGMII_FIBER (1G)
*/
+ switch_mac_mode = <8>;
+ sfp_tx_gpio = <27>;
+ sfp_rx_gpio = <29>;
};
};
Change-Id: I507be2b84b1f932802659abffa3288e304e0d411
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
This patch removes the support for dumpinfo_s structure to have
uniform EBICS0 bin for both sec and non-sec boots as the Read As Zero
(RAZ) flag has been enabled to protect code and data regions of TZ
The patchset applies to all the targets except IPQ5018 as the RAZ
flag enablement was not supported in IPQ5018
Change-Id: I63514284448de08926cd2c9b741f02859067044d
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
The CRASHDUMP RESET bit of TCSR_BOOT_MISC_DETECT Register
has to be set before reset from u-boot in the
crashdump collection path for TZ to differentiate between the
normal reset and crashdump reset from u-boot and
to retain the crash reason.
Change-Id: Ib623bfeab15d1bc230f4a8824218f1a3c4368fbb
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
Add support for ECO bit toggle during IPC start/stop
messages to allow BT subsystem to do self reset
Change-Id: I4d1d31a43ea8a002eb91cc42300677339c117d71
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
TCSR_BOOT_MISC_REG bits are not properly managed
for DLOAD implementation. Modify only necessary
bits to enable availability for new feature
implementations using TCSR_BOOT_MISC_REG.
Change-Id: I888a1bf6ce3654b0453c9ec2f87b4d5ff2a20de0
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
