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ipq5332: Update reset seq & MDIO clk for MHT

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Change-Id: I4ef6b84348289caf26768286b57252de88f8b3cc
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy 2022-11-18 13:32:47 +05:30 • committed by Gerrit - the friendly Code Review server
parent b6f164cdea
commit a2076a35ce
5 changed files with 14 additions and 2 deletions
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2
arch/arm/dts/ipq5332-mi01.2.dts
View file

@ -181,7 +181,7 @@
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_10GBASE_R>;
qca808x_gpio = <16>;
qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>;
mdc_mdio_gpio = <27 28>;
qca8084_switch_enable = <1>;

2
arch/arm/dts/ipq5332-mi01.4.dts
View file

@ -166,7 +166,7 @@
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII_PLUS>;
qca808x_gpio = <16>;
qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>;
mdc_mdio_gpio = <27 28>;
napa_gpio = <22>;

1
arch/arm/include/asm/arch-ipq5332/clk.h
View file

@ -173,6 +173,7 @@
#define NSS_CC_PORT1_RX_CBCR 0x39B00480
#define NSS_CC_UNIPHY_PORT1_RX_CBCR 0x39B004B4
#define MDIO_50MHZ_CLK_BASE 0x7a00610
#define GCC_USB_BCR 0x182C000
#define GCC_USB0_MASTER_CMD_RCGR 0x182C004

10
board/qca/arm/ipq5332/clock.c
View file

@ -484,6 +484,16 @@ void mdio_clock_init(void)
/* MDIO Master Clock init */
reg_val = readl(GCC_MDIO_MASTER_AHB_CBCR);
writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MDIO_MASTER_AHB_CBCR);
/* Enable 50MHZ */
reg_val = readl(MDIO_50MHZ_CLK_BASE);
reg_val |= BIT(0);
writel(reg_val, MDIO_50MHZ_CLK_BASE);
reg_val = readl(MDIO_50MHZ_CLK_BASE + 0x10000);
reg_val |= BIT(0);
writel(reg_val, MDIO_50MHZ_CLK_BASE + 0x10000);
}

1
board/qca/arm/ipq5332/ipq5332.c
View file

@ -870,6 +870,7 @@ void qca808x_phy_reset_init(void)
qca808x_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(qca808x_gpio[i]);
cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP;
writel(cfg, qca808x_gpio_base);
gpio_set_value(qca808x_gpio[i], 0x0);
}
}
}