mirror/u-boot-2016
1
0
Fork 0
mirror of https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git synced 2025-12-10 07:44:53 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

ipq: Remove runtime failsafe feature

Browse source 
Runtime failsafe feature is obsolete.
So reverting the same.

Change-Id: I2d3585bf756e3c717461ea5411b4d3fbb8659916
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
This commit is contained in:
Gokul Sriram Palanisamy 2022-11-09 17:32:22 +05:30 • committed by Gerrit - the friendly Code Review server
parent 69b77084fc
commit 60b84b15e8
17 changed files with 21 additions and 345 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

117
arch/arm/cpu/armv7/qca/common/smem.c
View file

@ -38,11 +38,6 @@
#include "fdt_info.h"
#include <ubi_uboot.h>
#include <command.h>
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
#include <sdhci.h>
#include <mmc.h>
#endif
#ifdef IPQ_UBI_VOL_WRITE_SUPPORT
static struct ubi_device *ubi;
@ -150,12 +145,6 @@ static struct smem *smem = (void *)(CONFIG_QCA_SMEM_BASE);
qca_smem_flash_info_t qca_smem_flash_info;
qca_smem_bootconfig_info_t qca_smem_bootconfig_info;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
unsigned ipq_runtime_failsafe_status;
unsigned ipq_runtime_fs_skip_status_check = 0;
unsigned ipq_runtime_fs_feature_enabled = 0;
#endif
#ifdef CONFIG_SMEM_VERSION_C
#define SMEM_COMMON_HOST 0xFFFE
@ -532,122 +521,16 @@ int smem_bootconfig_info(void)
return 0;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int smem_runtime_failsafe_info(void)
{
unsigned ret;
ret = smem_read_alloc_entry(SMEM_RUNTIME_FAILSAFE_INFO,
&ipq_runtime_failsafe_status, sizeof(ipq_runtime_failsafe_status));
if (ret != 0) {
printf("\nsmem: Failed to fetch the runtime failsafe status.." \
"Disabling the feature.\n");
ipq_runtime_fs_feature_enabled = 0;
}
if (ipq_runtime_failsafe_status & IPQ_RUNTIME_FAILSAFE_ENABLED) {
printf("\nRuntime Failsafe Feature Enabled\n");
ipq_runtime_fs_feature_enabled = 1;
}
return 0;
}
#endif
#ifndef CONFIG_SDHCI_SUPPORT
extern qca_mmc mmc_host;
#else
extern struct sdhci_host mmc_host;
#endif
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int smem_update_bootconfig_to_flash(void)
{
unsigned i, j, len;
uint32_t load_addr = 0;
char *part_name[] = {"0:BOOTCONFIG", "0:BOOTCONFIG1"};
char runcmd[256];
if (smem_runtime_failsafe_info() != 0)
return -ENOMSG;
if (ipq_runtime_fs_feature_enabled == 0)
return 0;
/* Update BOOTCONFIG in flash only if there is an update in SMEM by SBL */
if (!ipq_runtime_fs_skip_status_check) {
if (ipq_runtime_failsafe_status & IPQ_RUNTIME_FS_BOOTCONFIG_UPDATED) {
printf("\nRuntime hang detected: Partitions switched by SBL.\n");
} else {
return 0;
}
}
if ((qca_smem_bootconfig_info.magic_start != _SMEM_DUAL_BOOTINFO_MAGIC_START) &&
(qca_smem_bootconfig_info.magic_start != _SMEM_DUAL_BOOTINFO_MAGIC_START_TRYMODE)) {
if(smem_bootconfig_info() != 0)
return -1;
}
fs_debug("\nFailsafe: SMEM bootinfo from SBL: ");
for (j = 0; j < qca_smem_bootconfig_info.numaltpart; j++)
fs_debug("\nPartition: %s primaryboot = %d\n",
qca_smem_bootconfig_info.per_part_entry[j].name,
qca_smem_bootconfig_info.per_part_entry[j].primaryboot);
len = sizeof(part_name)/sizeof(part_name[0]);
load_addr = (uint32_t)&qca_smem_bootconfig_info;
for (i = 0; i < len; i++) {
snprintf(runcmd, sizeof(runcmd), "setenv fileaddr 0x%x && \
setenv filesize %d && flash %s",
load_addr, sizeof(qca_smem_bootconfig_info), part_name[i]);
if (run_command(runcmd, 0) != CMD_RET_SUCCESS)
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
__weak int is_hlos_crashed(void)
{
return 0;
}
void update_hlos_rootfs_primaryboot(void)
{
unsigned int i;
qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
fs_debug("\nFailsafe: %s: HLOS bit is SET", __func__);
printf("\nHLOS runtime hang detected: Switching Partitions.\n");
for (i = 0; i < qca_smem_bootconfig_info.numaltpart; i++) {
if (sfi->flash_type == SMEM_BOOT_MMC_FLASH ||
sfi->flash_type == SMEM_BOOT_SPI_FLASH) {
/* Note: SBL swaps the offsets for NAND case */
if (strncmp("0:HLOS", qca_smem_bootconfig_info.per_part_entry[i].name,
ALT_PART_NAME_LENGTH) == 0)
qca_smem_bootconfig_info.per_part_entry[i].primaryboot = 1;
if (strncmp("rootfs", qca_smem_bootconfig_info.per_part_entry[i].name,
ALT_PART_NAME_LENGTH) == 0)
qca_smem_bootconfig_info.per_part_entry[i].primaryboot = 1;
}
}
ipq_runtime_fs_skip_status_check = 1;
}
#endif
unsigned int get_rootfs_active_partition(void)
{
int i;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
if (ipq_runtime_fs_feature_enabled && is_hlos_crashed()) {
update_hlos_rootfs_primaryboot();
smem_update_bootconfig_to_flash();
}
#endif
for (i = 0; i < qca_smem_bootconfig_info.numaltpart; i++) {
if (strncmp("rootfs", qca_smem_bootconfig_info.per_part_entry[i].name,
ALT_PART_NAME_LENGTH) == 0)

1
arch/arm/include/asm/arch-qca-common/qca_common.h
View file

@ -104,7 +104,6 @@ void dump_func(unsigned int dump_level);
int do_dumpqca_flash_data(const char *);
int do_dumpqca_usb_data(unsigned int dump_level);
int apps_iscrashed(void);
int is_hlos_crashed(void);
int ipq_read_tcsr_boot_misc(void);
int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_flag);

3
arch/arm/include/asm/arch-qca-common/smem.h
View file

@ -132,7 +132,6 @@ typedef struct
extern qca_smem_bootconfig_info_t qca_smem_bootconfig_info;
int smem_bootconfig_info(void);
int smem_update_bootconfig_to_flash(void);
unsigned int get_smem_spi_addr_len(void);
unsigned int get_rootfs_active_partition(void);
unsigned int get_mibib_active_partition(void);
@ -140,6 +139,4 @@ void qca_smem_part_to_mtdparts(char *mtdid, int len);
int ipq_smem_get_socinfo_cpu_type(uint32_t *cpu_type);
int ipq_smem_get_socinfo_version(uint32_t *version);
int ipq_smem_get_boot_flash(uint32_t *flash_type);
int write_to_flash(int flash_type, uint32_t address, uint32_t offset,
uint32_t part_size, uint32_t file_size, char *layout);
#endif

16
arch/arm/lib/bootm.c
View file

@ -33,7 +33,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct tag *params;
extern unsigned ipq_runtime_fs_feature_enabled;
static ulong get_sp(void)
{
@ -278,21 +277,6 @@ struct aarch64_hdr {
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
unsigned int cookie, ret;
if (ipq_runtime_fs_feature_enabled) {
cookie = ipq_read_tcsr_boot_misc();
cookie &= ~IPQ_FS_NONHLOS_BIT;
cookie |= IPQ_FS_HLOS_BIT;
fs_debug("\nFailsafe: %s: Clear NonHLOS bit and set HLOS bit\n", __func__);
ret = qca_scm_dload(cookie);
if (ret)
printf ("Error in setting HLOS failsafe bit\n");
}
#endif
#ifdef CONFIG_ARM64
void (*kernel_entry)(void *fdt_addr, void *res0, void *res1,
void *res2);

8
board/qca/arm/common/fdt_fixup.c
View file

@ -918,11 +918,6 @@ __weak void fdt_fixup_sdx65_gpio(void *blob)
return;
}
__weak void fdt_fixup_runtime_failsafe(void *blob)
{
return;
}
__weak void ipq_fdt_fixup_usb_device_mode(void *blob)
{
const char *usb_cfg;
@ -1169,9 +1164,6 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_low_memory_fixup(blob);
fdt_fixup_qpic(blob);
fdt_fixup_qpic_serial_training_offset(blob);
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
fdt_fixup_runtime_failsafe(blob);
#endif
s = getenv("dload_warm_reset");
if (s)
fdt_fixup_set_dload_warm_reset(blob);

4
board/qca/arm/ipq5018/ipq5018.c
View file

@ -434,9 +434,9 @@ int ipq_read_tcsr_boot_misc(void)
int apps_iscrashed(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_MAGIC_COOKIE)
if (dmagic & DLOAD_MAGIC_COOKIE)
return 1;
return 0;

16
board/qca/arm/ipq5332/ipq5332.c
View file

@ -650,9 +650,9 @@ int ipq_read_tcsr_boot_misc(void)
int apps_iscrashed_crashdump_disabled(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_DISABLED)
if (dmagic & DLOAD_DISABLED)
return 1;
return 0;
@ -660,9 +660,9 @@ int apps_iscrashed_crashdump_disabled(void)
int apps_iscrashed(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_MAGIC_COOKIE)
if (dmagic & DLOAD_MAGIC_COOKIE)
return 1;
return 0;
@ -674,14 +674,6 @@ void reset_crashdump(void)
unsigned int cookie = 0;
cookie = ipq_read_tcsr_boot_misc();
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
if (ipq_runtime_fs_feature_enabled) {
fs_debug("\nFailsafe: %s: Clearing DLOAD and NonHLOS bits\n",
__func__);
cookie &= ~(DLOAD_BITS);
cookie &= ~(IPQ_FS_NONHLOS_BIT);
}
#endif
qca_scm_sdi();
cookie &= DLOAD_DISABLE;
ret = qca_scm_dload(cookie);

65
board/qca/arm/ipq6018/ipq6018.c
View file

@ -28,11 +28,9 @@
#include <i2c.h>
#include <dm.h>
#include <command.h>
#include <watchdog.h>
#define DLOAD_MAGIC_COOKIE 0x10
#define DLOAD_DISABLED 0x40
#define DLOAD_BITS 0xFF
#define TCSR_SOC_HW_VERSION_REG 0x194D000
@ -47,8 +45,6 @@ const char *del_node[] = {"uboot",
NULL};
const add_node_t add_fdt_node[] = {{}};
static int aq_phy_initialised;
extern unsigned ipq_runtime_fs_feature_enabled;
struct dumpinfo_t dumpinfo_n[] = {
/* TZ stores the DDR physical address at which it stores the
* APSS regs, UTCM copy dump. We will have the TZ IMEM
@ -114,31 +110,6 @@ void qca_serial_init(struct ipq_serial_platdata *plat)
return;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
void fdt_fixup_runtime_failsafe(void *blob)
{
int node_off, ret;
const char *fs_node = {"/soc/qti,scm_restart_reason"};
/* This fixup is for informing HLOS whether
* runtime failsafe feature is enabled or not
*/
node_off = fdt_path_offset(blob, fs_node);
if (node_off < 0) {
printf("%s: Failsafe: unable to find node '%s'\n",
__func__, fs_node);
return;
}
ret = fdt_setprop_u32(blob, node_off, "qti,runtime-failsafe",
ipq_runtime_fs_feature_enabled);
if (ret) {
printf("%s : Unable to set property 'ipq,runtime_failsafe'\n",__func__);
return;
}
}
#endif
int do_pmic_reset()
{
struct udevice *bus, *dev;
@ -173,29 +144,13 @@ int do_pmic_reset()
return 0;
}
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
writel(1, APCS_WDT_RST);
}
#endif
void reset_crashdump(void)
{
unsigned int ret = 0;
unsigned int cookie = 0;
cookie = ipq_read_tcsr_boot_misc();
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
if (ipq_runtime_fs_feature_enabled) {
fs_debug("\nFailsafe: %s: Clearing DLOAD and NonHLOS bits\n",
__func__);
cookie &= ~(DLOAD_BITS);
cookie &= ~(IPQ_FS_NONHLOS_BIT);
}
#endif
qca_scm_sdi();
cookie &= DLOAD_DISABLE;
ret = qca_scm_dload(cookie);
if (ret)
@ -802,23 +757,11 @@ int ipq_read_tcsr_boot_misc(void)
return *dmagic;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int is_hlos_crashed(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
if (*dmagic & IPQ_FS_HLOS_BIT)
return 1;
return 0;
}
#endif
int apps_iscrashed_crashdump_disabled(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_DISABLED)
if (dmagic & DLOAD_DISABLED)
return 1;
return 0;
@ -826,9 +769,9 @@ int apps_iscrashed_crashdump_disabled(void)
int apps_iscrashed(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_MAGIC_COOKIE)
if (dmagic & DLOAD_MAGIC_COOKIE)
return 1;
return 0;

7
board/qca/arm/ipq6018/ipq6018.h
View file

@ -263,8 +263,6 @@
#define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3)
#define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4)
#define APCS_WDT_RST 0xB017004
unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int,
unsigned int, unsigned int);
@ -367,10 +365,9 @@ typedef enum {
SMEM_BOOT_DUALPARTINFO = 503,
SMEM_PARTITION_TABLE_OFFSET = 504,
SMEM_SPI_FLASH_ADDR_LEN = 505,
SMEM_RUNTIME_FAILSAFE_INFO = 507,
SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
SMEM_LAST_VALID_TYPE = SMEM_RUNTIME_FAILSAFE_INFO,
SMEM_MAX_SIZE = SMEM_RUNTIME_FAILSAFE_INFO + 1,
SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN,
SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
} smem_mem_type_t;
extern const char *rsvd_node;

4
board/qca/arm/ipq807x/ipq807x.c
View file

@ -1754,9 +1754,9 @@ int ipq_read_tcsr_boot_misc(void)
int apps_iscrashed(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_MAGIC_COOKIE)
if (dmagic & DLOAD_MAGIC_COOKIE)
return 1;
return 0;

63
board/qca/arm/ipq9574/ipq9574.c
View file

@ -27,11 +27,9 @@
#include <mmc.h>
#include <sdhci.h>
#include <usb.h>
#include <watchdog.h>
#define DLOAD_MAGIC_COOKIE 0x10
#define DLOAD_DISABLED 0x40
#define DLOAD_BITS 0xFF
DECLARE_GLOBAL_DATA_PTR;
@ -41,7 +39,6 @@ extern int ipq_spi_init(u16);
unsigned int qpic_frequency = 0, qpic_phase = 0;
static int aq_phy_initialised = 0;
extern unsigned ipq_runtime_fs_feature_enabled;
extern int qca_scm_dpr(u32, u32, void *, size_t);
@ -63,31 +60,6 @@ void qca_serial_init(struct ipq_serial_platdata *plat)
return;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
void fdt_fixup_runtime_failsafe(void *blob)
{
int node_off, ret;
const char *fs_node = {"/soc/qti,scm_restart_reason"};
/* This fixup is for informing HLOS whether
* runtime failsafe feature is enabled or not
*/
node_off = fdt_path_offset(blob, fs_node);
if (node_off < 0) {
printf("%s: Failsafe: unable to find node '%s'\n",
__func__, fs_node);
return;
}
ret = fdt_setprop_u32(blob, node_off, "qti,runtime-failsafe",
ipq_runtime_fs_feature_enabled);
if (ret) {
printf("%s : Unable to set property 'ipq,runtime_failsafe'\n",__func__);
return;
}
}
#endif
void board_nand_init(void)
{
#ifdef CONFIG_QPIC_SERIAL
@ -1176,27 +1148,12 @@ unsigned long timer_read_counter(void)
return 0;
}
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
writel(1, APCS_WDT_RST);
}
#endif
void reset_crashdump(void)
{
unsigned int ret = 0;
unsigned int cookie = 0;
cookie = ipq_read_tcsr_boot_misc();
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
if (ipq_runtime_fs_feature_enabled) {
fs_debug("\nFailsafe: %s: Clearing DLOAD and NonHLOS bits\n",
__func__);
cookie &= ~(DLOAD_BITS);
cookie &= ~(IPQ_FS_NONHLOS_BIT);
}
#endif
qca_scm_sdi();
if (cookie & DLOAD_ENABLE) {
cookie |= CRASHDUMP_RESET;
@ -1286,23 +1243,11 @@ int ipq_read_tcsr_boot_misc(void)
return *dmagic;
}
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
int is_hlos_crashed(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
if (*dmagic & IPQ_FS_HLOS_BIT)
return 1;
return 0;
}
#endif
int apps_iscrashed_crashdump_disabled(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_DISABLED)
if (dmagic & DLOAD_DISABLED)
return 1;
return 0;
@ -1310,9 +1255,9 @@ int apps_iscrashed_crashdump_disabled(void)
int apps_iscrashed(void)
{
u32 *dmagic = TCSR_BOOT_MISC_REG;
u32 dmagic = ipq_read_tcsr_boot_misc();
if (*dmagic & DLOAD_MAGIC_COOKIE)
if (dmagic & DLOAD_MAGIC_COOKIE)
return 1;
return 0;

7
board/qca/arm/ipq9574/ipq9574.h
View file

@ -123,8 +123,6 @@
#define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3)
#define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4)
#define APCS_WDT_RST 0xB017004
/*
* GCC-QPIC Registers
*/
@ -373,10 +371,9 @@ typedef enum {
SMEM_BOOT_DUALPARTINFO = 503,
SMEM_PARTITION_TABLE_OFFSET = 504,
SMEM_SPI_FLASH_ADDR_LEN = 505,
SMEM_RUNTIME_FAILSAFE_INFO = 507,
SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
SMEM_LAST_VALID_TYPE = SMEM_RUNTIME_FAILSAFE_INFO,
SMEM_MAX_SIZE = SMEM_RUNTIME_FAILSAFE_INFO + 1,
SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN,
SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
} smem_mem_type_t;
#define MSM_SDC1_BASE 0x7800000

19
common/autoboot.c
View file

@ -15,12 +15,10 @@
#include <post.h>
#include <u-boot/sha256.h>
#include <asm/arch-qca-common/qca_common.h>
#include <asm/arch-qca-common/scm.h>
DECLARE_GLOBAL_DATA_PTR;
extern int do_dumpqca_minimal_data(const char *offset);
extern unsigned ipq_runtime_fs_feature_enabled;
#define MAX_DELAY_STOP_STR 32
@ -227,9 +225,6 @@ static int abortboot_normal(int bootdelay)
{
int abort = 0;
unsigned long ts;
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
unsigned int cookie, ret;
#endif
#ifdef CONFIG_MENUPROMPT
printf(CONFIG_MENUPROMPT);
@ -260,20 +255,6 @@ static int abortboot_normal(int bootdelay)
if (tstc()) { /* we got a key press */
abort = 1; /* don't auto boot */
bootdelay = 0; /* no more delay */
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
if (ipq_runtime_fs_feature_enabled) {
cookie = ipq_read_tcsr_boot_misc();
cookie &= ~IPQ_FS_NONHLOS_BIT;
fs_debug("\nFailsafe: %s: Clear NonHLOS bit\n", __func__);
ret = qca_scm_dload(cookie);
if (ret)
printf ("Error in SCM to clear NonHLOS failsafe bit\n");
}
#endif
# ifdef CONFIG_MENUKEY
menukey = getc();
# else

6
common/board_r.c
View file

@ -64,9 +64,6 @@
#ifdef CONFIG_AVR32
#include <asm/arch/mmu.h>
#endif
#if defined(CONFIG_IPQ_RUNTIME_FAILSAFE)
#include <asm/arch-qca-common/smem.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -954,9 +951,6 @@ init_fnc_t init_sequence_r[] = {
#endif
#if defined(CONFIG_SPARC)
prom_init,
#endif
#if defined(CONFIG_IPQ_RUNTIME_FAILSAFE)
smem_update_bootconfig_to_flash,
#endif
run_main_loop,
};

2
common/cmd_flashwrite.c
View file

@ -48,7 +48,7 @@ struct header {
} __attribute__ ((__packed__));
#endif
int write_to_flash(int flash_type, uint32_t address, uint32_t offset,
static int write_to_flash(int flash_type, uint32_t address, uint32_t offset,
uint32_t part_size, uint32_t file_size, char *layout)
{

12
include/configs/ipq6018.h
View file

@ -295,18 +295,6 @@ extern loff_t board_env_size;
#define DLOAD_DISABLE (~BIT(4))
#define DLOAD_ENABLE BIT(4)
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
#define CONFIG_HW_WATCHDOG
#define IPQ_FS_NONHLOS_BIT (1 << 10)
#define IPQ_FS_HLOS_BIT (1 << 11)
#endif
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE_DEBUG
#define fs_debug(fmt, args...) printf(fmt, ##args);
#else
#define fs_debug(fmt, args...)
#endif
/*
* Below Configs need to be updated after enabling reset_crashdump
* Included now to avoid build failure

16
include/configs/ipq9574.h
View file

@ -295,22 +295,6 @@ extern loff_t board_env_size;
#define DLOAD_ENABLE BIT(4)
#define CRASHDUMP_RESET BIT(11)
#define CONFIG_IPQ_RUNTIME_FAILSAFE
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE
#define CONFIG_HW_WATCHDOG
#define IPQ_FS_NONHLOS_BIT (1 << 10)
#define IPQ_FS_HLOS_BIT (1 << 11)
#define IPQ_RUNTIME_FAILSAFE_ENABLED (1 << 0)
#define IPQ_RUNTIME_FS_BOOTCONFIG_UPDATED (1 << 1)
#endif
#ifdef CONFIG_IPQ_RUNTIME_FAILSAFE_DEBUG
#define fs_debug(fmt, args...) printf(fmt, ##args);
#else
#define fs_debug(fmt, args...)
#endif
/*
* Below Configs need to be updated after enabling reset_crashdump
* Included now to avoid build failure