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Merge "board: arm: ipq5332: update eMMC clock sequence"

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Linux Build Service Account 2022-10-21 00:31:51 -07:00 • committed by Gerrit - the friendly Code Review server
commit 942cca269f
5 changed files with 44 additions and 46 deletions
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6
arch/arm/dts/ipq5332-soc.dtsi
View file

@ -69,7 +69,7 @@
0x20300000 0xd00000
0x20100000 0x100000
0x1829000 0x60
0x8c000 0x1000>;
0x4B0000 0x800>;
reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
"axi_conf", "pci_rst", "pci_phy";
gen3 = <1>;
@ -88,7 +88,7 @@
0x18300000 0xd00000
0x18100000 0x100000
0x1828000 0x60
0xF4000 0x1000>;
0x4B1000 0x1000>;
reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
"axi_conf", "pci_rst", "pci_phy";
gen3 = <1>;
@ -107,7 +107,7 @@
0x10300000 0xd00000
0x10100000 0x100000
0x182A000 0x60
0xFC000 0x1000>;
0x4B1800 0x800>;
reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
"axi_conf", "pci_rst", "pci_phy";
gen3 = <1>;

19
arch/arm/include/asm/arch-ipq5332/clk.h
View file

@ -89,14 +89,17 @@
* GCC-SDCC Registers
*/
#define GCC_SDCC1_BCR 0x01833000
#define GCC_SDCC1_APPS_CMD_RCGR 0x01833004
#define GCC_SDCC1_APPS_CFG_RCGR 0x01833008
#define GCC_SDCC1_APPS_M 0x0183300C
#define GCC_SDCC1_APPS_N 0x01833010
#define GCC_SDCC1_APPS_D 0x01833014
#define GCC_SDCC1_APPS_CBCR 0x01833034
#define GCC_SDCC1_AHB_CBCR 0x0183301C
#define GCC_SDCC1_BCR 0x1833000
#define GCC_SDCC1_APPS_CMD_RCGR 0x1833004
#define GCC_SDCC1_APPS_CFG_RCGR 0x1833008
#define GCC_SDCC1_APPS_M 0x183300C
#define GCC_SDCC1_APPS_N 0x1833010
#define GCC_SDCC1_APPS_D 0x1833014
#define GCC_SDCC1_APPS_CBCR 0x183302C
#define GCC_SDCC1_AHB_CBCR 0x1833034
#define GCC_SDCC1_APPS_CFG_RCGR_MODE_SEL (2 << 12)
#define GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL (2 << 8)
#define GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV (0xB << 0)
/*
* Ethernet Clocks

37
board/qca/arm/ipq5332/clock.c
View file

@ -85,27 +85,26 @@ int uart_clock_config(struct ipq_serial_platdata *plat)
void emmc_clock_init(void)
{
#ifdef QCA_CLOCK_ENABLE
/* Enable root clock generator */
writel(readl(GCC_SDCC1_APPS_CBCR)|0x1, GCC_SDCC1_APPS_CBCR);
/* Add 10us delay for CLK_OFF to get cleared */
udelay(10);
writel(readl(GCC_SDCC1_AHB_CBCR)|0x1, GCC_SDCC1_AHB_CBCR);
/* PLL0 - 192Mhz */
writel(0x20B, GCC_SDCC1_APPS_CFG_RCGR);
/* Delay for clock operation complete */
udelay(10);
writel(0x1, GCC_SDCC1_APPS_M);
/* check this M, N D value while debugging
* because as per clock tool the actual M, N, D
* values are M=1, N=FA, D=F9
int cfg;
/* Configure sdcc1_apps_clk_src */
cfg = (GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL |
GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV |
GCC_SDCC1_APPS_CFG_RCGR_MODE_SEL);
writel(cfg, GCC_SDCC1_APPS_CFG_RCGR);
/*
* Mode is dual edge,
* For 192Mhz doesn't require MND value
* 1152 / 6 = 192
*/
writel(0xFC, GCC_SDCC1_APPS_N);
writel(0xFD, GCC_SDCC1_APPS_D);
/* Delay for clock operation complete */
writel(CMD_UPDATE, GCC_SDCC1_APPS_CMD_RCGR);
mdelay(10);
writel(ROOT_EN, GCC_SDCC1_APPS_CMD_RCGR);
/* Configure CBCRs */
writel(readl(GCC_SDCC1_APPS_CBCR) | CLK_ENABLE, GCC_SDCC1_APPS_CBCR);
udelay(10);
/* Update APPS_CMD_RCGR to reflect source selection */
writel(readl(GCC_SDCC1_APPS_CMD_RCGR)|0x1, GCC_SDCC1_APPS_CMD_RCGR);
/* Add 10us delay for clock update to complete */
writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
udelay(10);
#else
return;

23
board/qca/arm/ipq5332/ipq5332.c
View file

@ -443,10 +443,9 @@ void board_pci_init(int id)
void board_pci_deinit()
{
int node, gpio_node, i, err, is_x2;
int node, gpio_node, i, err;
char name[16];
struct fdt_resource parf;
struct fdt_resource pci_phy;
for (i = 0; i < PCI_MAX_DEVICES; i++) {
snprintf(name, sizeof(name), "pci%d", i);
@ -457,22 +456,14 @@ void board_pci_deinit()
}
err = fdt_get_named_resource(gd->fdt_blob, node, "reg",
"reg-names", "parf", &parf);
writel(0x0, parf.start + 0x358);
writel(0x1, parf.start + 0x40);
err = fdt_get_named_resource(gd->fdt_blob, node, "reg",
"reg-names", "pci_phy", &pci_phy);
if (err < 0)
if (err < 0) {
printf("Unable to find parf node for PCIE%d \n", i);
continue;
}
if ((i == 0) || (i == 1))
is_x2 = 0;
else
is_x2 = 1;
writel(0x1, pci_phy.start + (0x800 + (0x800 * is_x2)));
writel(0x0, pci_phy.start + (0x804 + (0x800 * is_x2)));
writel(0x0, parf.start + PCIE_PARF_SLV_ADDR_SPACE_SIZE);
writel(PCIE_PHY_TEST_PWR_DOWN,
parf.start + PCIE_PARF_PHY_CTRL);
gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "pci_gpio");
if (gpio_node >= 0)

5
board/qca/arm/ipq5332/ipq5332.h
View file

@ -143,6 +143,11 @@ enum pcie_port_lane_mode_t{
#define PCIE_1_CLOCK_DISABLE_BIT 12
#define PCIE_2_CLOCK_DISABLE_BIT 10
#define PCIE_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define PCIE_PARF_PHY_CTRL 0x40
#define PCIE_PHY_TEST_PWR_DOWN 0x1
/*
* GPIO functional configs
*/