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arm: dts: ipq5332: update pcie aux clock source as xo

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The pcie AUX clock source changed to XO as per
GCC frequency plan

Change-Id: If032831d3a9523ec214a62cbed2950ee5839920e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This commit is contained in:
Timple Raj M 2022-11-25 16:15:59 +05:30 • committed by Gerrit - the friendly Code Review server
parent de09c34cc9
commit a148c9c8e4
2 changed files with 6 additions and 6 deletions
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6
arch/arm/include/asm/arch-ipq5332/clk.h
View file

@ -314,9 +314,9 @@
#define GCC_PCIE3X1_1_RCHG_CMD_RCGR (GCC_PCIE3X1_1_BASE+0x078)
#define GCC_PCIE3X1_1_RCHG_CFG_RCGR (GCC_PCIE3X1_1_BASE+0x07C)
#define GCC_PCIE_AUX_CFG_RCGR_MN_MODE (2 << 12)
#define GCC_PCIE_AUX_CFG_RCGR_SRC_SEL (2 << 8)
#define GCC_PCIE_AUX_CFG_RCGR_SRC_DIV (0x1F << 0)
#define GCC_PCIE_AUX_CFG_RCGR_MN_MODE (0 << 12)
#define GCC_PCIE_AUX_CFG_RCGR_SRC_SEL (0 << 8) /* SRC = XO */
#define GCC_PCIE_AUX_CFG_RCGR_SRC_DIV (0x17 << 0)
#define GCC_PCIE_AXI_CFG_RCGR_SRC_SEL (0x9 << 0)
#define GCC_PCIE_AXI_CFG_RCGR_SRC_DIV (2 << 8)

6
board/qca/arm/ipq5332/clock.c
View file

@ -136,9 +136,9 @@ void pcie_v2_clock_init(int pcie_id)
GCC_PCIE_AUX_CFG_RCGR_SRC_SEL |
GCC_PCIE_AUX_CFG_RCGR_SRC_DIV);
writel(cfg, GCC_PCIE_AUX_CFG_RCGR);
writel(0x1, GCC_PCIE_AUX_M);
writel(0xFFE7, GCC_PCIE_AUX_N);
writel(0xFFE6, GCC_PCIE_AUX_D);
writel(0, GCC_PCIE_AUX_M);
writel(0, GCC_PCIE_AUX_N);
writel(0, GCC_PCIE_AUX_D);
writel(CMD_UPDATE, GCC_PCIE_AUX_CMD_RCGR);
mdelay(10);
writel(ROOT_EN, GCC_PCIE_AUX_CMD_RCGR);