mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-06 01:11:47 +01:00
board: arm: ipq5332: update ethernet clock config
Change-Id: I3354354c7cffcb3107293efc54834c5d87556518 Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy
Gerrit - the friendly Code Review server
parent
390ce51a5e
commit
e3b2150af9
2 changed files with 138 additions and 79 deletions
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@ -104,8 +104,49 @@
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/*
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* Ethernet Clocks
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*/
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#define GCC_QDSS_AT_CMD_RCGR 0x0182D004
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#define GCC_QDSS_AT_CFG_RCGR 0x0182D008
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#define QDSS_AT_SRC_SEL 1 << 8
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#define QDSS_AT_DIV_SEL 9 << 8
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#define GCC_PCNOC_BFDCD_CFG_RCGR 0x1831008
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#define GCC_PCNOC_BFDCD_CMD_RCGR 0x1831004
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#define PCCNOC_BFDCD_SRC_SEL 1 << 8
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#define PCCNOC_BFDCD_DIV_SEL 0xF << 0
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#define GCC_SYSTEM_NOC_BFDCD_CFG_RCGR 0x182E008
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#define GCC_SYSTEM_NOC_BFDCD_CMD_RCGR 0x182E004
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#define SYSTEM_NOC_BFDCD_SRC_SEL 2 << 8
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#define SYSTEM_NOC_BFDCD_DIV_SEL 8 << 0
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#define NSS_CC_PPE_CMD_RCGR 0x39B003E8
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#define NSS_CC_PPE_CFG_RCGR 0x39B003EC
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#define NSS_CC_PPE_SRC_SEL 0x6 << 8
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#define NSS_CC_PPE_DIV_SEL 1 << 0
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#define GCC_IM_SLEEP_CBCR 0x1834020
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#define NSS_CC_NSS_CSR_CBCR 0x39B005E8
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#define NSS_CC_NSSNOC_NSS_CSR_CBCR 0x39B005EC
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#define GCC_UNIPHY0_SYS_CBCR 0x181600C
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#define GCC_UNIPHY1_SYS_CBCR 0x1816018
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#define GCC_UNIPHY1_AHB_CBCR 0x181601C
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#define GCC_UNIPHY0_AHB_CBCR 0x1816010
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#define NSS_CC_NSSNOC_PPE_CBCR 0x39B00420
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#define GCC_MDIO_SLAVE_AHB_CBCR 0x181200C
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#define GCC_MDIO_MASTER_AHB_CBCR 0x1812004
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#define GCC_NSSCC_CBCR 0x1817034
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#define GCC_NSSNOC_NSSCC_CBCR 0x1817030
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#define PLL_POWER_ON_AND_RESET 0x9B780
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#define PLL_REFERENCE_CLOCK 0x9B784
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#define FREQUENCY_MASK 0xfffffdf0
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#define INTERNAL_48MHZ_CLOCK 0x7
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#define NSS_CC_CFG_CMD_RCGR 0x39B005E0
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#define NSS_CC_CFG_CFG_RCGR 0x39B005E4
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#define NSS_CC_SRC_SEL 2 << 8
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#define NSS_CC_DIV_SEL 0xF << 0
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#define GCC_UNIPHY_SYS_ADDR 0x0181600C
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#define GCC_NSSNOC_ATB_CLK 0x01817014
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#define GCC_NSSNOC_QOSGEN_REF_CLK 0x0181701C
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#define GCC_NSSNOC_TIMEOUT_REF_CLK 0x01817020
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@ -332,90 +332,71 @@ void usb_clock_deinit(void)
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#endif
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#ifdef CONFIG_IPQ5332_EDMA
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void nssnoc_init(void){
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unsigned int gcc_qdss_at_cmd_rcgr_addr = 0x182D004;
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writel(0x109, gcc_qdss_at_cmd_rcgr_addr + 4);
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writel(0x1, gcc_qdss_at_cmd_rcgr_addr);
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/* Enable required NSSNOC clocks */
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writel(readl(GCC_NSSCFG_CLK) | GCC_CBCR_CLK_ENABLE, GCC_NSSCFG_CLK);
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writel(readl(GCC_NSSNOC_ATB_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_ATB_CLK);
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writel(readl(GCC_NSSNOC_QOSGEN_REF_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_QOSGEN_REF_CLK);
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writel(readl(GCC_NSSNOC_TIMEOUT_REF_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_NSSNOC_TIMEOUT_REF_CLK);
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}
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void frequency_init(void)
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{
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unsigned int nss_cc_cfg_addr;
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unsigned int gcc_uniphy_sys_addr;
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unsigned int gcc_pcnoc_addr;
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unsigned int gcc_sysnoc_addr;
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unsigned int reg_val;
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/* GCC NSS frequency 100M */
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nss_cc_cfg_addr = 0x39B005E0;
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reg_val = readl(nss_cc_cfg_addr + 4);
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reg_val = readl(NSS_CC_CFG_CFG_RCGR);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x20f, nss_cc_cfg_addr + 4);
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writel(reg_val | NSS_CC_SRC_SEL | NSS_CC_DIV_SEL ,
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NSS_CC_CFG_CFG_RCGR);
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reg_val = readl(nss_cc_cfg_addr);
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writel(reg_val | 0x1, nss_cc_cfg_addr);
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reg_val = readl(NSS_CC_CFG_CMD_RCGR);
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writel(reg_val | CMD_UPDATE, NSS_CC_CFG_CMD_RCGR);
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mdelay(1);
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writel(reg_val | ROOT_EN, NSS_CC_CFG_CMD_RCGR);
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/* GCC CC PPE frequency 353M */
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reg_val = readl(NSS_CC_PPE_FREQUENCY_RCGR + 4);
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/* PCNOC_BFDCD frequency for Uniphy AHB 100M */
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reg_val = readl(GCC_PCNOC_BFDCD_CFG_RCGR);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x101, NSS_CC_PPE_FREQUENCY_RCGR + 4);
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writel(reg_val | PCCNOC_BFDCD_SRC_SEL | PCCNOC_BFDCD_DIV_SEL,
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GCC_PCNOC_BFDCD_CFG_RCGR);
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reg_val = readl(GCC_PCNOC_BFDCD_CMD_RCGR);
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writel(reg_val | CMD_UPDATE, GCC_PCNOC_BFDCD_CMD_RCGR);
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mdelay(1);
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writel(reg_val | ROOT_EN, GCC_PCNOC_BFDCD_CMD_RCGR);
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reg_val = readl(NSS_CC_PPE_FREQUENCY_RCGR);
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writel(reg_val | 0x1, NSS_CC_PPE_FREQUENCY_RCGR);
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/* Uniphy SYS 24M */
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gcc_uniphy_sys_addr = 0x1816004;
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reg_val = readl(gcc_uniphy_sys_addr + 4);
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/* SYSNOC frequency 266.666667M */
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reg_val = readl(GCC_SYSTEM_NOC_BFDCD_CFG_RCGR);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x1, gcc_uniphy_sys_addr + 4);
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/* Update Config */
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reg_val = readl(gcc_uniphy_sys_addr);
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writel(reg_val | 0x1, gcc_uniphy_sys_addr);
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writel(reg_val | SYSTEM_NOC_BFDCD_SRC_SEL | SYSTEM_NOC_BFDCD_DIV_SEL,
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GCC_SYSTEM_NOC_BFDCD_CFG_RCGR);
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/* PCNOC frequency for Uniphy AHB 100M */
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gcc_pcnoc_addr = 0x1831004;
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reg_val = readl(gcc_pcnoc_addr + 4);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x10F, gcc_pcnoc_addr + 4);
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/* Update Config */
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reg_val = readl(gcc_pcnoc_addr);
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writel(reg_val | 0x1, gcc_pcnoc_addr);
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reg_val = readl(GCC_SYSTEM_NOC_BFDCD_CMD_RCGR);
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writel(reg_val | CMD_UPDATE, GCC_SYSTEM_NOC_BFDCD_CMD_RCGR);
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mdelay(1);
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writel(reg_val | ROOT_EN, GCC_SYSTEM_NOC_BFDCD_CMD_RCGR);
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/* SYSNOC frequency 343M */
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gcc_sysnoc_addr = 0x182E004;
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reg_val = readl(gcc_sysnoc_addr + 4);
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/* Port Clock rate 200M */
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reg_val = readl(NSS_CC_PPE_CFG_RCGR);
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reg_val &= ~0x7ff;
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writel(reg_val | 0x206, gcc_sysnoc_addr + 4);
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/* Update Config */
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reg_val = readl(gcc_sysnoc_addr);
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writel(reg_val | 0x1, gcc_sysnoc_addr);
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writel(reg_val | NSS_CC_PPE_SRC_SEL | NSS_CC_PPE_DIV_SEL,
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NSS_CC_PPE_CFG_RCGR);
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reg_val = readl( NSS_CC_PPE_CMD_RCGR);
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writel(reg_val | CMD_UPDATE, NSS_CC_PPE_CMD_RCGR);
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mdelay(1);
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writel(reg_val | ROOT_EN, NSS_CC_PPE_CMD_RCGR);
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reg_val = readl(GCC_NSSCC_CBCR);
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writel(reg_val | CLK_ENABLE, GCC_NSSCC_CBCR);
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reg_val = readl(GCC_NSSNOC_NSSCC_CBCR);
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writel(reg_val | CLK_ENABLE, GCC_NSSNOC_NSSCC_CBCR);
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}
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void fixed_nss_csr_clock_init(void)
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{
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unsigned int gcc_nss_csr_addr;
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unsigned int reg_val;
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/* NSS CSR and NSSNOC CSR Clock init */
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gcc_nss_csr_addr = 0x39B005E8;
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reg_val = readl(gcc_nss_csr_addr);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, gcc_nss_csr_addr);
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/* NSSNOC CSR */
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reg_val = readl(gcc_nss_csr_addr + 0x4);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, gcc_nss_csr_addr + 0x4);
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reg_val = readl(NSS_CC_NSSNOC_NSS_CSR_CBCR);
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writel(reg_val | CLK_ENABLE, NSS_CC_NSSNOC_NSS_CSR_CBCR);
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reg_val = readl(NSS_CC_NSS_CSR_CBCR);
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writel(reg_val | CLK_ENABLE, NSS_CC_NSS_CSR_CBCR);
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}
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void fixed_sys_clock_init(void)
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@ -424,6 +405,10 @@ void fixed_sys_clock_init(void)
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/* SYS Clock init */
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/* Enable AHB and SYS clk of CMN */
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reg_val = readl(GCC_IM_SLEEP_CBCR);
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writel(reg_val | CLK_ENABLE, GCC_IM_SLEEP_CBCR);
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reg_val = readl(GCC_CMN_BLK_ADDR + GCC_CMN_BLK_AHB_CBCR_OFFSET);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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GCC_CMN_BLK_ADDR + GCC_CMN_BLK_AHB_CBCR_OFFSET);
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@ -435,19 +420,20 @@ void fixed_sys_clock_init(void)
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void fixed_uniphy_clock_init(void)
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{
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int i;
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unsigned int reg_val;
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/* Uniphy AHB AND SYS CBCR init */
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for (i = 0; i < 2; i++) {
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reg_val = readl(GCC_UNIPHY_SYS_ADDR + i*0x10);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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GCC_UNIPHY_SYS_ADDR + i*0x10);
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reg_val = readl(GCC_UNIPHY0_SYS_CBCR);
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writel(reg_val | CLK_ENABLE, GCC_UNIPHY0_SYS_CBCR);
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reg_val = readl((GCC_UNIPHY_SYS_ADDR + 0x4) + i*0x10);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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(GCC_UNIPHY_SYS_ADDR + 0x4) + i*0x10);
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}
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reg_val = readl(GCC_UNIPHY1_SYS_CBCR);
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writel(reg_val | CLK_ENABLE, GCC_UNIPHY1_SYS_CBCR);
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reg_val = readl(GCC_UNIPHY0_AHB_CBCR);
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writel(reg_val | CLK_ENABLE, GCC_UNIPHY0_AHB_CBCR);
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reg_val = readl(GCC_UNIPHY1_AHB_CBCR);
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writel(reg_val | CLK_ENABLE, GCC_UNIPHY1_AHB_CBCR);
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}
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void port_mac_clock_init(void)
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@ -458,7 +444,8 @@ void port_mac_clock_init(void)
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/* Port Mac Clock init */
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for (i = 0; i < 2; i++) {
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reg_val = readl(GCC_PORT_MAC_ADDR + i*0x8);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_PORT_MAC_ADDR + i*0x8);
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writel(reg_val | GCC_CBCR_CLK_ENABLE,
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GCC_PORT_MAC_ADDR + i*0x8);
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}
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}
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@ -499,6 +486,16 @@ void cfg_clock_init(void)
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writel(reg_val | GCC_CBCR_CLK_ENABLE, NSS_CC_PPE_SWITCH_BTQ_ADDR);
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}
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void mdio_clock_init(void)
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{
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unsigned int reg_val;
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/* MDIO Master Clock init */
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reg_val = readl(GCC_MDIO_MASTER_AHB_CBCR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MDIO_MASTER_AHB_CBCR);
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}
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void noc_clock_init(void)
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{
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unsigned int reg_val;
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@ -509,9 +506,6 @@ void noc_clock_init(void)
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reg_val = readl(GCC_NSSNOC_SNOC_1_CBCR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_NSSNOC_SNOC_1_CBCR);
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reg_val = readl(GCC_MEM_NOC_SNOC_AXI_CBCR);
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writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MEM_NOC_SNOC_AXI_CBCR);
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}
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void uniphy_clock_enable(enum uniphy_clk_type clk_type, bool enable)
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@ -557,15 +551,39 @@ void fixed_clock_init(void)
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cfg_clock_init();
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mdio_clock_init();
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noc_clock_init();
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}
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void cmbblk_init(void)
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{
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#ifndef CONFIG_IPQ5332_RUMI
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unsigned int reg_val;
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reg_val = readl(PLL_REFERENCE_CLOCK);
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reg_val = (reg_val & FREQUENCY_MASK) | INTERNAL_48MHZ_CLOCK;
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writel(reg_val, PLL_REFERENCE_CLOCK);
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reg_val = readl(PLL_POWER_ON_AND_RESET);
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reg_val = reg_val | 0x40;
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writel(reg_val, PLL_POWER_ON_AND_RESET);
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mdelay(10);
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reg_val = reg_val & (~0x40);
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writel(reg_val, PLL_POWER_ON_AND_RESET);
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mdelay(10);
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writel(0xbf, PLL_POWER_ON_AND_RESET);
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mdelay(10);
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writel(0xff, PLL_POWER_ON_AND_RESET);
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mdelay(10);
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#endif
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}
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void eth_clock_init(void)
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{
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nssnoc_init();
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fixed_clock_init();
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uniphy_clk_init(true);
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cmbblk_init();
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}
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#endif
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