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board: qca: arm: ipq5332: Enable gcc_blsp1_ahb_clk

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When xbl logs are disabled no logs came in uart console
due to gcc_blsp1_ahb_clk in disabled state.
This patch enables gcc_blsp1_ahb_clk in u-boot to avoid this issue.

Change-Id: I161b003096544e54d3d230027c2665e8fa3d0f5e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This commit is contained in:
Timple Raj M 2022-12-26 16:14:49 +05:30
parent 47e8f38182
commit a7dcdb2f7c
2 changed files with 6 additions and 0 deletions
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2
arch/arm/include/asm/arch-ipq5332/clk.h
View file

@ -21,6 +21,7 @@
/*
* UART registers
*/
#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x180B004
#define GCC_BLSP1_UART1_BCR 0x1802028
#define GCC_BLSP1_UART2_BCR 0x1803028
#define GCC_BLSP1_UART3_BCR 0x1804028
@ -44,6 +45,7 @@
#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
#define BLSP1_AHB_CLK_ENABLE 0x16
#define UART_RCGR_SRC_SEL 0x1
#define UART_RCGR_SRC_DIV 0x0
#define UART_RCGR_MODE 0x2

4
board/qca/arm/ipq5332/clock.c
View file

@ -64,6 +64,10 @@ int uart_clock_config(struct ipq_serial_platdata *plat)
unsigned long cbcr_val;
int ret;
cbcr_val = readl(GCC_APCS_CLOCK_BRANCH_ENA_VOTE);
cbcr_val |= BLSP1_AHB_CLK_ENABLE;
writel(cbcr_val, GCC_APCS_CLOCK_BRANCH_ENA_VOTE);
uart_configure_mux(plat->port_id);
writel(plat->m_value, GCC_BLSP1_UART_APPS_M(plat->port_id));