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arm: dts: ipq5332: Enabled i2c usb and pci

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This patch enables i2c usb and pci in AP-MI01.2 and AP-MI01.4.

Change-Id: I4f09485fcbad4247aa75676cb72dc4345405fdfc
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This commit is contained in:
Timple Raj M 2022-11-30 11:40:08 +05:30
parent 24f263d138
commit a2fbc4b3bc
4 changed files with 8 additions and 14 deletions
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2
arch/arm/dts/ipq5332-mi01.2.dts
View file

@ -47,7 +47,7 @@
};
};
i2c {
i2c@78B6000 {
i2c_gpio {
gpio1 {
gpio = <29>;

10
arch/arm/dts/ipq5332-mi01.4.dts
View file

@ -23,9 +23,9 @@
console = "/serial@78AF000";
nand = "/nand-controller@79B0000";
mmc = "/sdhci@7804000";
usb0 = "xhci@8a00000";
i2c0 = "/i2c@78B6000";
usb0 = "/xhci@8a00000";
pci1 = "/pci@18000000";
i2c0 = "/i2c@78B6000";
};
serial@78AF000 {
@ -46,7 +46,7 @@
};
};
i2c {
i2c@78B6000 {
i2c_gpio {
gpio1 {
gpio = <29>;
@ -148,6 +148,10 @@
};
};
usb0: xhci@8a00000 {
ssphy = <1>;
};
pci1: pci@18000000 {
status = "ok";
perst_gpio = <47>;

8
board/qca/arm/ipq5332/ipq5332.c
View file

@ -584,14 +584,6 @@ static void usb_init_ssphy(void __iomem *phybase)
writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR);
writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
udelay(100);
/*set frequency initial value*/
writel(0x1cb9, phybase + SSCG_CTRL_REG_4);
writel(0x023a, phybase + SSCG_CTRL_REG_5);
/*set spectrum spread count*/
writel(0xd360, phybase + SSCG_CTRL_REG_3);
/*set fstep*/
writel(0x1, phybase + SSCG_CTRL_REG_1);
writel(0xeb, phybase + SSCG_CTRL_REG_2);
return;
}

2
board/qca/arm/ipq5332/ipq5332.h
View file

@ -39,8 +39,6 @@ extern const add_node_t add_fdt_node[];
#define TCSR_MODE_CTRL_2PORT_2LANE 0x1947544
#define USB30_GUCTL 0x8A0C12C
#define DLOAD_MAGIC_COOKIE 0x10
#define DLOAD_DISABLED 0x40
#define DLOAD_BITS 0xFF