mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-11 03:28:39 +01:00
board: arm: ipq5332: update ethernet configuration
Change-Id: If66707a68ddf5681016acd95332d4056b31fb3fc Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy
Gerrit - the friendly Code Review server
parent
e3b2150af9
commit
bc5f3cca5a
6 changed files with 609 additions and 519 deletions
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@ -905,14 +905,76 @@ void qca808x_phy_reset_init_done(void)
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}
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}
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int get_sfp_gpio(int sfp_gpio[2])
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{
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int sfp_gpio_cnt = -1, node;
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int res = -1;
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node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
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if (node >= 0) {
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sfp_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node,
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"sfp_gpio_cnt", -1);
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if (sfp_gpio_cnt >= 1) {
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res = fdtdec_get_int_array(gd->fdt_blob, node,
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"sfp_gpio",
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(u32 *)sfp_gpio,
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sfp_gpio_cnt);
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if (res >= 0)
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return sfp_gpio_cnt;
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}
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}
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return res;
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}
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void sfp_reset_init(void)
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{
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int sfp_gpio[2] = {-1, -1}, sfp_gpio_cnt, i;
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unsigned int *sfp_gpio_base;
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uint32_t cfg;
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sfp_gpio_cnt = get_sfp_gpio(sfp_gpio);
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if (sfp_gpio_cnt >= 1) {
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for (i = 0; i < sfp_gpio_cnt; i++) {
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if (sfp_gpio[i] >= 0) {
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sfp_gpio_base =
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(unsigned int *)GPIO_CONFIG_ADDR(
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sfp_gpio[i]);
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cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP;
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writel(cfg, sfp_gpio_base);
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}
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}
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}
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}
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void qca8081_napa_reset(void)
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{
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unsigned int *napa_gpio_base;
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int node, gpio;
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uint32_t cfg;
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node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
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if (node >= 0) {
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gpio = fdtdec_get_uint(gd->fdt_blob, node , "napa_gpio", -1);
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if (gpio != -1) {
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napa_gpio_base =
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(unsigned int *)GPIO_CONFIG_ADDR(gpio);
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cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP;
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writel(cfg, napa_gpio_base);
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mdelay(100);
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gpio_set_value(gpio, 0x1);
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}
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}
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}
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void bring_phy_out_of_reset(void)
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{
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qca8081_napa_reset();
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aquantia_phy_reset_init();
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qca808x_phy_reset_init();
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sfp_reset_init();
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mdelay(500);
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aquantia_phy_reset_init_done();
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qca808x_phy_reset_init_done();
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mdelay(500);
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}
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void ipq5332_eth_initialize(void)
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File diff suppressed because it is too large
Load diff
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@ -82,7 +82,8 @@ void ppe_ipo_action_set(union ipo_action_u *hw_act, int rule_id)
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}
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}
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void ipq5332_ppe_acl_set(int rule_id, int rule_type, int field0, int field1, int mask, int permit, int deny)
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void ipq5332_ppe_acl_set(int rule_id, int rule_type, int field0, int field1,
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int mask, int permit, int deny)
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{
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union ipo_rule_reg_u hw_reg = {0};
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union ipo_mask_reg_u hw_mask = {0};
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@ -198,14 +199,16 @@ void ppe_port_bridge_txmac_set(int port_id, int status)
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uint32_t reg_value = 0;
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ipq5332_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS +
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(port_id * PORT_BRIDGE_CTRL_INC), ®_value);
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((port_id * PORT_BRIDGE_CTRL_INC) + PORT_BRIDGE_CTRL_INC),
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®_value);
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if (status == 0)
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reg_value |= TX_MAC_EN;
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else
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reg_value &= ~TX_MAC_EN;
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ipq5332_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS +
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(port_id * PORT_BRIDGE_CTRL_INC), reg_value);
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((port_id * PORT_BRIDGE_CTRL_INC) + PORT_BRIDGE_CTRL_INC),
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reg_value);
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}
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@ -221,8 +224,10 @@ void ppe_port_txmac_status_set(uint32_t port)
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ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);
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pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
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pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address"
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" = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
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reg_value);
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}
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@ -233,7 +238,8 @@ void ppe_port_rxmac_status_set(uint32_t port)
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pr_debug("DEBUGGING rxmac_status_set......... PORTID = %d\n", port);
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ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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MAC_RX_CONFIGURATION_ADDRESS +
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(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), ®_value);
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(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION),
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®_value);
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reg_value |= 0x300000c0;
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reg_value |=RE;
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@ -241,9 +247,11 @@ void ppe_port_rxmac_status_set(uint32_t port)
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reg_value |=CST;
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ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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MAC_RX_CONFIGURATION_ADDRESS +
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(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), reg_value);
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(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION),
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reg_value);
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pr_debug("NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION Address = 0x%x -> Value = %u\n",
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pr_debug("NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION Address"
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" = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_RX_CONFIGURATION_ADDRESS +
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(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION),
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reg_value);
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@ -251,11 +259,12 @@ void ppe_port_rxmac_status_set(uint32_t port)
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void ppe_mac_packet_filter_set(uint32_t port)
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{
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pr_debug("DEBUGGING mac_packet_filter_set......... PORTID = %d\n", port);
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pr_debug("DEBUGGING mac_packet_filter_set...... PORTID = %d\n", port);
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ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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MAC_PACKET_FILTER_ADDRESS +
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(port * MAC_PACKET_FILTER_INC), 0x80000081);
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pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address = 0x%x -> Value = %u\n",
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pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address"
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" = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_PACKET_FILTER_ADDRESS +
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(port * MAC_PACKET_FILTER_ADDRESS),
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0x80000081);
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@ -267,43 +276,28 @@ void ppe_mac_packet_filter_set(uint32_t port)
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*/
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void ipq5332_port_mac_clock_reset(int port)
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{
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int reg_val, reg_val1;
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int reg_val;
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reg_val = readl(NSS_CC_PPE_RESET_ADDR);
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reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
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switch(port) {
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case 0:
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/* Assert */
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reg_val |= GCC_PPE_PORT1_MAC_ARES;
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reg_val1 |= GCC_PORT1_ARES;
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writel(reg_val, NSS_CC_PPE_RESET_ADDR);
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writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
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mdelay(150);
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/* De-Assert */
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reg_val = readl(NSS_CC_PPE_RESET_ADDR);
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reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
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reg_val &= ~GCC_PPE_PORT1_MAC_ARES;
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reg_val1 &= ~GCC_PORT1_ARES;
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break;
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case 1:
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/* Assert */
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reg_val |= GCC_PPE_PORT2_MAC_ARES;
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reg_val1 |= GCC_PORT2_ARES;
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writel(reg_val, NSS_CC_PPE_RESET_ADDR);
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writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
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mdelay(150);
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/* De-Assert */
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reg_val = readl(NSS_CC_PPE_RESET_ADDR);
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reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
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reg_val &= ~GCC_PPE_PORT2_MAC_ARES;
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reg_val1 &= ~GCC_PORT2_ARES;
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break;
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default:
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break;
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}
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writel(reg_val, NSS_CC_PPE_RESET_ADDR);
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writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
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mdelay(150);
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/* PPE Reset */
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writel(0x1, NSS_CC_PPE_BCR);
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udelay(10);
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writel(0x0, NSS_CC_PPE_BCR);
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reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8));
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reg_val |= GCC_PORT1_ARES;
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writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8));
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mdelay(10);
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reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8));
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reg_val &= ~GCC_PORT1_ARES;
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writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + (port * 0x8));
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reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8));
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reg_val |= GCC_PORT1_ARES;
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writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8));
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mdelay(10);
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reg_val = readl(NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8));
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reg_val &= ~GCC_PORT1_ARES;
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writel(reg_val, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (port * 0x8));
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}
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void ipq5332_speed_clock_set(int port_id, int clk[4])
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@ -313,14 +307,15 @@ void ipq5332_speed_clock_set(int port_id, int clk[4])
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for (i = 0; i < 6; i++)
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{
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reg_val[i] = readl(NSS_CC_PORT1_RX_CMD_RCGR + (i * 0x4) + (port_id * 0x18));
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reg_val[i] = readl(NSS_CC_PORT1_RX_CMD_RCGR + (i * 0x4) +
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(port_id * 0x18));
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}
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reg_val[0] &= ~0x1;
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reg_val[1] &= ~0x71f;
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reg_val[2] &= ~0x1ff;
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reg_val[2] &= ~0xf;
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reg_val[3] &= ~0x1;
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reg_val[4] &= ~0x71f;
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reg_val[5] &= ~0x1ff;
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reg_val[5] &= ~0xf;
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reg_val[1] |= clk[0];
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reg_val[2] |= clk[1];
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@ -334,7 +329,8 @@ void ipq5332_speed_clock_set(int port_id, int clk[4])
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/* Port Tx direction speed clock cfg */
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writel(reg_val[4], NSS_CC_PORT1_RX_CMD_RCGR + 0x10 + (port_id * 0x18));
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writel(reg_val[5], NSS_CC_PORT1_RX_CMD_RCGR + 0x14 + (port_id * 0x18));
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writel(reg_val[3] | 0x1, NSS_CC_PORT1_RX_CMD_RCGR + 0xc + (port_id * 0x18));
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writel(reg_val[3] | 0x1, NSS_CC_PORT1_RX_CMD_RCGR + 0xc +
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(port_id * 0x18));
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}
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int phy_status_get_from_ppe(int port_id)
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@ -342,10 +338,9 @@ int phy_status_get_from_ppe(int port_id)
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uint32_t reg_field = 0;
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ipq5332_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, ®_field);
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if (port_id == (PORT5 - PPE_UNIPHY_INSTANCE1))
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reg_field >>= PORT_PHY_STATUS_PORT5_1_OFFSET;
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else
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reg_field >>= PORT_PHY_STATUS_PORT6_OFFSET;
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if (port_id == 1)
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reg_field >>= PORT_PHY_STATUS_PORT2_OFFSET;
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return ((reg_field >> 7) & 0x1) ? 0 : 1;
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}
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@ -362,15 +357,17 @@ void ppe_xgmac_10g_r_speed_set(uint32_t port)
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ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);
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pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
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reg_value);
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pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x"
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"-> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
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reg_value);
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}
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void ipq5332_10g_r_speed_set(int port, int status)
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{
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ppe_xgmac_10g_r_speed_set(port);
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ppe_port_bridge_txmac_set(port + 1, status);
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ppe_port_bridge_txmac_set(port, status);
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ppe_port_txmac_status_set(port);
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ppe_port_rxmac_status_set(port);
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ppe_mac_packet_filter_set(port);
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@ -408,12 +405,15 @@ void ppe_xgmac_speed_set(uint32_t port, int speed)
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reg_value |=JD;
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ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);
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pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
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reg_value);
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pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x"
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" -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
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reg_value);
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}
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void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
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int status)
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{
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@ -433,7 +433,7 @@ void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
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ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex);
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ppe_uniphy_usxgmii_port_reset(uniphy_index);
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#endif
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ppe_port_bridge_txmac_set(port + 1, status);
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ppe_port_bridge_txmac_set(port, status);
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ppe_port_txmac_status_set(port);
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ppe_port_rxmac_status_set(port);
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ppe_mac_packet_filter_set(port);
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@ -441,7 +441,7 @@ void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
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void ipq5332_pqsgmii_speed_set(int port, int speed, int status)
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{
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ppe_port_bridge_txmac_set(port + 1, status);
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ppe_port_bridge_txmac_set(port, status);
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ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_SPEED + (0x200 * port), speed);
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ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_ENABLE + (0x200 * port), 0x73);
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ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
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@ -464,12 +464,12 @@ static void ipq5332_ppe_flow_port_map_tbl_port_num_set(int queue, int port)
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static void ipq5332_ppe_flow_map_tbl_set(int queue, int port)
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{
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uint32_t val = port | 0x401000; /* c_drr_wt = 1, e_drr_wt = 1 */
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ipq5332_ppe_reg_write(IPQ5332_PPE_L0_FLOW_MAP_TBL + queue * IPQ5332_PPE_L0_FLOW_MAP_TBL_INC,
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val);
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ipq5332_ppe_reg_write(IPQ5332_PPE_L0_FLOW_MAP_TBL + queue *
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IPQ5332_PPE_L0_FLOW_MAP_TBL_INC, val);
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val = port | 0x100400; /* c_drr_wt = 1, e_drr_wt = 1 */
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ipq5332_ppe_reg_write(IPQ5332_PPE_L1_FLOW_MAP_TBL + port * IPQ5332_PPE_L1_FLOW_MAP_TBL_INC,
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val);
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ipq5332_ppe_reg_write(IPQ5332_PPE_L1_FLOW_MAP_TBL + port *
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IPQ5332_PPE_L1_FLOW_MAP_TBL_INC, val);
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}
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/*
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@ -477,6 +477,38 @@ static void ipq5332_ppe_flow_map_tbl_set(int queue, int port)
|
|||
*/
|
||||
static void ipq5332_ppe_tdm_configuration(void)
|
||||
{
|
||||
#ifndef CONFIG_IPQ5332_RUMI
|
||||
ipq5332_ppe_reg_write(0xc000, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc010, 0x30);
|
||||
ipq5332_ppe_reg_write(0xc020, 0x21);
|
||||
ipq5332_ppe_reg_write(0xc030, 0x31);
|
||||
ipq5332_ppe_reg_write(0xc040, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc050, 0x32);
|
||||
ipq5332_ppe_reg_write(0xc060, 0x20);
|
||||
ipq5332_ppe_reg_write(0xc070, 0x30);
|
||||
ipq5332_ppe_reg_write(0xc080, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc090, 0x31);
|
||||
ipq5332_ppe_reg_write(0xc0a0, 0x21);
|
||||
ipq5332_ppe_reg_write(0xc0b0, 0x32);
|
||||
ipq5332_ppe_reg_write(0xc0c0, 0x20);
|
||||
ipq5332_ppe_reg_write(0xc0d0, 0x30);
|
||||
ipq5332_ppe_reg_write(0xc0e0, 0x21);
|
||||
ipq5332_ppe_reg_write(0xc0f0, 0x31);
|
||||
ipq5332_ppe_reg_write(0xc100, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc110, 0x32);
|
||||
ipq5332_ppe_reg_write(0xc120, 0x20);
|
||||
ipq5332_ppe_reg_write(0xc130, 0x30);
|
||||
ipq5332_ppe_reg_write(0xc140, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc150, 0x31);
|
||||
ipq5332_ppe_reg_write(0xc160, 0x21);
|
||||
ipq5332_ppe_reg_write(0xc170, 0x32);
|
||||
ipq5332_ppe_reg_write(0xc180, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc190, 0x30);
|
||||
ipq5332_ppe_reg_write(0xc1a0, 0x20);
|
||||
ipq5332_ppe_reg_write(0xc1b0, 0x31);
|
||||
ipq5332_ppe_reg_write(0xc1c0, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc1d0, 0x32);
|
||||
#else
|
||||
ipq5332_ppe_reg_write(0xc000, 0x20);
|
||||
ipq5332_ppe_reg_write(0xc010, 0x32);
|
||||
ipq5332_ppe_reg_write(0xc020, 0x21);
|
||||
|
|
@ -484,11 +516,11 @@ static void ipq5332_ppe_tdm_configuration(void)
|
|||
ipq5332_ppe_reg_write(0xc040, 0x22);
|
||||
ipq5332_ppe_reg_write(0xc050, 0x31);
|
||||
ipq5332_ppe_reg_write(0xb000, 0x80000006);
|
||||
|
||||
ipq5332_ppe_reg_write(0x47a000, 0xfa10);
|
||||
ipq5332_ppe_reg_write(0x47a010, 0xfc21);
|
||||
ipq5332_ppe_reg_write(0x47a020, 0xf902);
|
||||
ipq5332_ppe_reg_write(0x400000, 0x3);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -585,8 +617,10 @@ static void ipq5332_ppe_enable_port_counter(void)
|
|||
*/
|
||||
static void ipq5332_ppe_c_sp_cfg_tbl_drr_id_set(int id)
|
||||
{
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L0_C_SP_CFG_TBL + (id * 0x80), id * 2);
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L1_C_SP_CFG_TBL + (id * 0x80), id * 2);
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L0_C_SP_CFG_TBL +
|
||||
(id * 0x80), id * 2);
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L1_C_SP_CFG_TBL +
|
||||
(id * 0x80), id * 2);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -594,8 +628,10 @@ static void ipq5332_ppe_c_sp_cfg_tbl_drr_id_set(int id)
|
|||
*/
|
||||
static void ipq5332_ppe_e_sp_cfg_tbl_drr_id_set(int id)
|
||||
{
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L0_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L1_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L0_E_SP_CFG_TBL +
|
||||
(id * 0x80), id * 2 + 1);
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_L1_E_SP_CFG_TBL +
|
||||
(id * 0x80), id * 2 + 1);
|
||||
}
|
||||
|
||||
static void ppe_port_mux_set(int port_id, int port_type, int mode)
|
||||
|
|
@ -611,13 +647,14 @@ static void ppe_port_mux_set(int port_id, int port_type, int mode)
|
|||
else if (port_type == PORT_XGMAC_TYPE)
|
||||
mux_mac_type = IPQ5332_PORT_MUX_XMAC_TYPE;
|
||||
else
|
||||
printf("\nAttention!!!..Port type configured wrongly..port_id = %d, mode = %d, port_type = %d",
|
||||
port_id, mode, port_type);
|
||||
printf("\nAttention!!!..Port type configured wrongly.."
|
||||
"port_id = %d, mode = %d, port_type = %d",
|
||||
port_id, mode, port_type);
|
||||
|
||||
port_mux_ctrl.val = 0;
|
||||
ipq5332_ppe_reg_read(IPQ5332_PORT_MUX_CTRL, &(port_mux_ctrl.val));
|
||||
pr_debug("\nBEFORE UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val);
|
||||
|
||||
pr_debug("\nBEFORE UPDATE: Port MUX CTRL value is %u",
|
||||
port_mux_ctrl.val);
|
||||
|
||||
switch (port_id) {
|
||||
case PORT1:
|
||||
|
|
@ -633,7 +670,8 @@ static void ppe_port_mux_set(int port_id, int port_type, int mode)
|
|||
}
|
||||
|
||||
ipq5332_ppe_reg_write(IPQ5332_PORT_MUX_CTRL, port_mux_ctrl.val);
|
||||
pr_debug("\nAFTER UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val);
|
||||
pr_debug("\nAFTER UPDATE: Port MUX CTRL value is %u",
|
||||
port_mux_ctrl.val);
|
||||
}
|
||||
|
||||
void ppe_port_mux_mac_type_set(int port_id, int mode)
|
||||
|
|
@ -653,8 +691,9 @@ void ppe_port_mux_mac_type_set(int port_id, int mode)
|
|||
port_type = PORT_XGMAC_TYPE;
|
||||
break;
|
||||
default:
|
||||
printf("\nError during port_type set: mode is %d, port_id is: %d",
|
||||
mode, port_id);
|
||||
printf("\nError during port_type set: mode is %d, "
|
||||
"port_id is: %d",
|
||||
mode, port_id);
|
||||
return;
|
||||
}
|
||||
ppe_port_mux_set(port_id, port_type, mode);
|
||||
|
|
@ -701,6 +740,7 @@ void ipq5332_ppe_provision_init(void)
|
|||
{
|
||||
int i;
|
||||
uint32_t queue;
|
||||
uint32_t bridge_ctrl;
|
||||
|
||||
/* tdm/sched configuration */
|
||||
ipq5332_ppe_tdm_configuration();
|
||||
|
|
@ -709,28 +749,20 @@ void ipq5332_ppe_provision_init(void)
|
|||
/* Add CPU port 0 to VSI 2 */
|
||||
ipq5332_ppe_vp_port_tbl_set(0, 2);
|
||||
|
||||
/* Add port 1 - 4 to VSI 2 */
|
||||
/* Add port 1 - 2 to VSI 2 */
|
||||
ipq5332_ppe_vp_port_tbl_set(1, 2);
|
||||
ipq5332_ppe_vp_port_tbl_set(2, 2);
|
||||
ipq5332_ppe_vp_port_tbl_set(3, 2);
|
||||
ipq5332_ppe_vp_port_tbl_set(4, 2);
|
||||
ipq5332_ppe_vp_port_tbl_set(5, 2);
|
||||
ipq5332_ppe_vp_port_tbl_set(6, 2);
|
||||
|
||||
#else
|
||||
ipq5332_ppe_vp_port_tbl_set(1, 2);
|
||||
ipq5332_ppe_vp_port_tbl_set(2, 3);
|
||||
ipq5332_ppe_vp_port_tbl_set(3, 4);
|
||||
ipq5332_ppe_vp_port_tbl_set(4, 5);
|
||||
ipq5332_ppe_vp_port_tbl_set(5, 6);
|
||||
ipq5332_ppe_vp_port_tbl_set(6, 7);
|
||||
#endif
|
||||
|
||||
/* Unicast priority map */
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_QM_UPM_TBL, 0);
|
||||
|
||||
/* Port0 - 7 unicast queue settings */
|
||||
for (i = 0; i < 8; i++) {
|
||||
/* Port0 - 3 unicast queue settings */
|
||||
for (i = 0; i < 3; i++) {
|
||||
if (i == 0)
|
||||
queue = 0;
|
||||
else
|
||||
|
|
@ -748,7 +780,7 @@ void ipq5332_ppe_provision_init(void)
|
|||
ipq5332_ppe_reg_write(0x403000, 0x00401000);
|
||||
|
||||
/* Port1 - 7 multicast queue */
|
||||
for (i = 1; i < 8; i++) {
|
||||
for (i = 1; i < 3; i++) {
|
||||
ipq5332_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i);
|
||||
ipq5332_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i);
|
||||
}
|
||||
|
|
@ -771,57 +803,51 @@ void ipq5332_ppe_provision_init(void)
|
|||
/*
|
||||
* Port0 - TX_EN is set by default, Port1 - LRN_EN is set
|
||||
* Port0 -> CPU Port
|
||||
* Port1-6 -> Ethernet Ports
|
||||
* Port7 -> EIP197
|
||||
* Port1-2 -> Ethernet Ports
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (i == 0)
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
|
||||
for (i = 0; i < 3; i++) {
|
||||
bridge_ctrl = IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET;
|
||||
if (i == 0) {
|
||||
ipq5332_ppe_reg_write(bridge_ctrl + (i * 4),
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_TXMAC_EN |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
|
||||
else if (i == 7)
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
|
||||
else
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
|
||||
} else {
|
||||
ipq5332_ppe_reg_write(bridge_ctrl + (i * 4),
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
|
||||
IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP);
|
||||
}
|
||||
}
|
||||
|
||||
/* Global learning */
|
||||
ipq5332_ppe_reg_write(0x060038, 0xc0);
|
||||
|
||||
#ifdef CONFIG_IPQ5332_BRIDGED_MODE
|
||||
ipq5332_vsi_setup(2, 0x7f);
|
||||
ipq5332_vsi_setup(2, 0x7);
|
||||
#else
|
||||
ipq5332_vsi_setup(2, 0x03);
|
||||
ipq5332_vsi_setup(3, 0x05);
|
||||
ipq5332_vsi_setup(4, 0x09);
|
||||
ipq5332_vsi_setup(5, 0x11);
|
||||
ipq5332_vsi_setup(6, 0x21);
|
||||
ipq5332_vsi_setup(7, 0x41);
|
||||
#endif
|
||||
|
||||
/* Port 0-7 STP */
|
||||
for (i = 0; i < 8; i++)
|
||||
/* Port 0-3 STP */
|
||||
for (i = 0; i < 3; i++)
|
||||
ipq5332_ppe_reg_write(IPQ5332_PPE_STP_BASE + (0x4 * i), 0x3);
|
||||
|
||||
ipq5332_ppe_interface_mode_init();
|
||||
/* Port 1-2 disable */
|
||||
for (i = 0; i < 2; i++) {
|
||||
ipq5332_gmac_port_disable(i);
|
||||
ppe_port_bridge_txmac_set(i + 1, 1);
|
||||
ppe_port_bridge_txmac_set(i, 1);
|
||||
}
|
||||
|
||||
/* Allowing DHCP packets */
|
||||
ipq5332_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67, 0xffff, 0, 0);
|
||||
ipq5332_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68, 0xffff, 0, 0);
|
||||
ipq5332_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67,
|
||||
0xffff, 0, 0);
|
||||
ipq5332_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68,
|
||||
0xffff, 0, 0);
|
||||
/* Dropping all the UDP packets */
|
||||
ipq5332_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0, 1);
|
||||
ipq5332_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0,
|
||||
1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -115,9 +115,8 @@ union ipo_action_u {
|
|||
#define IPQ5332_PORT_MUX_CTRL_INC 0x4
|
||||
#define IPQ5332_PORT_MUX_CTRL_DEFAULT 0x0
|
||||
|
||||
#define PORT_PHY_STATUS_ADDRESS 0x44
|
||||
#define PORT_PHY_STATUS_PORT5_1_OFFSET 8
|
||||
#define PORT_PHY_STATUS_PORT6_OFFSET 16
|
||||
#define PORT_PHY_STATUS_ADDRESS 0x40
|
||||
#define PORT_PHY_STATUS_PORT2_OFFSET 8
|
||||
|
||||
#define IPQ5332_PPE_IPE_L3_BASE_ADDR 0x200000
|
||||
#define IPQ5332_PPE_L3_VP_PORT_TBL_ADDR (IPQ5332_PPE_IPE_L3_BASE_ADDR + 0x4000)
|
||||
|
|
@ -260,3 +259,7 @@ union ipo_action_u {
|
|||
|
||||
#define IPO_ACTION_ADDRESS 0x8000
|
||||
#define IPO_ACTION_INC 0x20
|
||||
|
||||
#define NSS_CC_PORT1_RX_CMD_RCGR 0x39B00450
|
||||
#define GCC_PORT1_ARES 1 << 2
|
||||
#define NSS_CC_PPE_BCR 0x39B003E4
|
||||
|
|
|
|||
|
|
@ -72,8 +72,9 @@ static int ppe_uniphy_calibration(uint32_t uniphy_index)
|
|||
printf("uniphy callibration time out!\n");
|
||||
return -1;
|
||||
}
|
||||
reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
+ PPE_UNIPHY_OFFSET_CALIB_4);
|
||||
reg_value = readl(PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
+ PPE_UNIPHY_OFFSET_CALIB_4);
|
||||
calibration_done = (reg_value >> 0x7) & 0x1;
|
||||
}
|
||||
|
||||
|
|
@ -82,70 +83,41 @@ static int ppe_uniphy_calibration(uint32_t uniphy_index)
|
|||
|
||||
static void ppe_uniphy_reset(enum uniphy_reset_type rst_type, bool enable)
|
||||
{
|
||||
uint32_t mode, node;
|
||||
uint32_t reg_val, reg_val1;
|
||||
uint32_t reg_val;
|
||||
|
||||
switch(rst_type) {
|
||||
case UNIPHY0_SOFT_RESET:
|
||||
node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
|
||||
if (node < 0) {
|
||||
printf("\nError: ess-switch not specified in dts");
|
||||
return;
|
||||
}
|
||||
mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1);
|
||||
if (mode < 0) {
|
||||
printf("\nError: switch_mac_mode1 not specified in dts");
|
||||
return;
|
||||
}
|
||||
reg_val = readl(GCC_UNIPHY0_MISC);
|
||||
reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
|
||||
if (mode == EPORT_WRAPPER_MAX) {
|
||||
if (enable) {
|
||||
reg_val |= 0x1;
|
||||
reg_val1 |= 0xffc000;
|
||||
} else {
|
||||
reg_val &= ~0x1;
|
||||
reg_val1 &= ~0xffc000;
|
||||
}
|
||||
reg_val = readl(GCC_UNIPHY0_SYS_CBCR);
|
||||
if (enable) {
|
||||
reg_val |= 0x4;
|
||||
} else {
|
||||
if (enable) {
|
||||
reg_val |= 0x1;
|
||||
reg_val1 |= 0xff0000;
|
||||
} else {
|
||||
reg_val &= ~0x1;
|
||||
reg_val1 &= ~0xff0000;
|
||||
}
|
||||
reg_val &= ~0x4;
|
||||
}
|
||||
writel(reg_val, GCC_UNIPHY0_MISC);
|
||||
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
|
||||
writel(reg_val, GCC_UNIPHY0_SYS_CBCR);
|
||||
break;
|
||||
case UNIPHY0_XPCS_RESET:
|
||||
reg_val = readl(GCC_UNIPHY0_MISC);
|
||||
if (enable)
|
||||
reg_val |= 0x4;
|
||||
reg_val |= 0x1;
|
||||
else
|
||||
reg_val &= ~0x4;
|
||||
reg_val &= ~0x1;
|
||||
writel(reg_val, GCC_UNIPHY0_MISC);
|
||||
break;
|
||||
case UNIPHY1_SOFT_RESET:
|
||||
reg_val = readl(GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC);
|
||||
reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
|
||||
reg_val = readl(GCC_UNIPHY1_SYS_CBCR);
|
||||
if (enable) {
|
||||
reg_val |= 0x1;
|
||||
reg_val1 |= 0xC000;
|
||||
reg_val |= 0x4;
|
||||
} else {
|
||||
reg_val &= ~0x1;
|
||||
reg_val1 &= ~0xC000;
|
||||
reg_val &= ~0x4;
|
||||
}
|
||||
writel(reg_val, GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC);
|
||||
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
|
||||
writel(reg_val, GCC_UNIPHY1_SYS_CBCR);
|
||||
break;
|
||||
case UNIPHY1_XPCS_RESET:
|
||||
reg_val = readl(GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC);
|
||||
if (enable)
|
||||
reg_val |= 0x4;
|
||||
reg_val |= 0x1;
|
||||
else
|
||||
reg_val &= ~0x4;
|
||||
reg_val &= ~0x1;
|
||||
writel(reg_val, GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC);
|
||||
break;
|
||||
default:
|
||||
|
|
@ -218,22 +190,27 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
|
|||
{
|
||||
if ((uniphy_index == 1) && (mode == EPORT_WRAPPER_SGMII_PLUS)) {
|
||||
writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET);
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) +
|
||||
UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET);
|
||||
|
||||
ppe_uniphy_set_forceMode(uniphy_index);
|
||||
|
||||
writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) +
|
||||
UNIPHY_MISC2_REG_OFFSET);
|
||||
} else {
|
||||
writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) +
|
||||
UNIPHY_MISC2_REG_OFFSET);
|
||||
}
|
||||
|
||||
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) +
|
||||
UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
mdelay(500);
|
||||
writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) +
|
||||
UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
mdelay(500);
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true);
|
||||
|
|
@ -248,23 +225,27 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
|
|||
|
||||
switch (mode) {
|
||||
case EPORT_WRAPPER_SGMII_FIBER:
|
||||
writel(0x400, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
writel(0x400, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
+ PPE_UNIPHY_MODE_CONTROL);
|
||||
break;
|
||||
|
||||
case EPORT_WRAPPER_SGMII0_RGMII4:
|
||||
case EPORT_WRAPPER_SGMII1_RGMII4:
|
||||
case EPORT_WRAPPER_SGMII4_RGMII4:
|
||||
writel(0x420, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
writel(0x420, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
+ PPE_UNIPHY_MODE_CONTROL);
|
||||
break;
|
||||
|
||||
case EPORT_WRAPPER_SGMII_PLUS:
|
||||
if (uniphy_index == 1)
|
||||
writel(0x20, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
writel(0x20, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
+ PPE_UNIPHY_MODE_CONTROL);
|
||||
else
|
||||
writel(0x820, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
writel(0x820, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
+ PPE_UNIPHY_MODE_CONTROL);
|
||||
break;
|
||||
|
||||
|
|
@ -347,10 +328,12 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
|
|||
writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
|
||||
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) +
|
||||
UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
mdelay(500);
|
||||
writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
(uniphy_index * PPE_UNIPHY_REG_INC) +
|
||||
UNIPHY_PLL_RESET_REG_OFFSET);
|
||||
mdelay(500);
|
||||
|
||||
if (uniphy_index == 0)
|
||||
|
|
|
|||
|
|
@ -72,6 +72,8 @@
|
|||
#define VR_MII_AN_INTR_STS 0x1f8002
|
||||
#define CL37_ANCMPLT_INTR (1 << 0)
|
||||
|
||||
#define GCC_UNIPHY0_MISC 0x1816050
|
||||
|
||||
enum uniphy_reset_type {
|
||||
UNIPHY0_SOFT_RESET = 0,
|
||||
UNIPHY0_XPCS_RESET,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue