mirror/u-boot-2016
1
0
Fork 0
mirror of https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git synced 2026-03-09 02:37:31 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge "board: qca: arm: ipq5332: Enable gcc_blsp1_ahb_clk"

Browse source
This commit is contained in:
Linux Build Service Account 2022-12-27 06:47:58 -08:00 • committed by Gerrit - the friendly Code Review server
commit 5287b8e49c
2 changed files with 6 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/include/asm/arch-ipq5332/clk.h
View file

@ -21,6 +21,7 @@
/*
* UART registers
*/
#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x180B004
#define GCC_BLSP1_UART1_BCR 0x1802028
#define GCC_BLSP1_UART2_BCR 0x1803028
#define GCC_BLSP1_UART3_BCR 0x1804028
@ -44,6 +45,7 @@
#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
#define BLSP1_AHB_CLK_ENABLE 0x16
#define UART_RCGR_SRC_SEL 0x1
#define UART_RCGR_SRC_DIV 0x0
#define UART_RCGR_MODE 0x2

4
board/qca/arm/ipq5332/clock.c
View file

@ -64,6 +64,10 @@ int uart_clock_config(struct ipq_serial_platdata *plat)
unsigned long cbcr_val;
int ret;
cbcr_val = readl(GCC_APCS_CLOCK_BRANCH_ENA_VOTE);
cbcr_val |= BLSP1_AHB_CLK_ENABLE;
writel(cbcr_val, GCC_APCS_CLOCK_BRANCH_ENA_VOTE);
uart_configure_mux(plat->port_id);
writel(plat->m_value, GCC_BLSP1_UART_APPS_M(plat->port_id));