mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-05 00:41:17 +01:00
board: ipq5332: remove rumi flags.
Change-Id: I84ae7f2c6e8852c879aebc3538a8782c5b335d28 Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy
parent
66dadd051f
commit
c77f44b731
3 changed files with 0 additions and 73 deletions
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@ -84,7 +84,6 @@ int uart_clock_config(struct ipq_serial_platdata *plat)
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void)
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{
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#ifdef QCA_CLOCK_ENABLE
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int cfg;
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/* Configure sdcc1_apps_clk_src */
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@ -111,9 +110,7 @@ void emmc_clock_init(void)
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udelay(10);
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writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
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udelay(10);
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#else
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return;
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#endif
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}
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void emmc_clock_reset(void)
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@ -126,7 +123,6 @@ void emmc_clock_reset(void)
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#ifdef CONFIG_PCI_IPQ
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void pcie_v2_clock_init(int pcie_id)
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{
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#ifdef QCA_CLOCK_ENABLE
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int cfg, cfg1,cfg2;
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static int clk_configure;
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@ -215,14 +211,11 @@ void pcie_v2_clock_init(int pcie_id)
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writel(CLK_ENABLE, GCC_SNOC_PCIE3_1LANE_S_CBCR);
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writel(CLK_ENABLE, GCC_SNOC_PCIE3_1LANE_1_M_CBCR);
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writel(CLK_ENABLE, GCC_SNOC_PCIE3_1LANE_1_S_CBCR);
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#else
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return;
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#endif
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}
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void pcie_v2_clock_deinit(int pcie_id)
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{
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#ifdef QCA_CLOCK_ENABLE
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writel(0x0, GCC_SNOC_PCIE3_2LANE_M_CBCR);
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writel(0x0, GCC_SNOC_PCIE3_2LANE_S_CBCR);
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writel(0x0, GCC_SNOC_PCIE3_1LANE_M_CBCR);
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@ -257,15 +250,12 @@ void pcie_v2_clock_deinit(int pcie_id)
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writel(0x0, GCC_PCIE3X1_1_AUX_CBCR);
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break;
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}
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#else
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return;
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#endif
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}
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#endif
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(void)
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{
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#ifdef QCA_CLOCK_ENABLE
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int cfg;
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/* Configure usb0_master_clk_src */
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@ -317,23 +307,18 @@ void usb_clock_init(void)
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writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_AUX_CBCR);
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writel(CLK_ENABLE, GCC_USB0_LFPS_CBCR);
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#else
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return;
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#endif
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}
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void usb_clock_deinit(void)
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{
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#ifdef QCA_CLOCK_ENABLE
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writel(0x0, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0x4220, GCC_USB0_MASTER_CBCR);
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writel(0x0, GCC_USB0_SLEEP_CBCR);
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writel(0x0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0x0, GCC_USB0_AUX_CBCR);
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writel(0x0, GCC_USB0_LFPS_CBCR);
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#else
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return;
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#endif
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}
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#endif
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@ -566,7 +551,6 @@ void fixed_clock_init(void)
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void cmbblk_init(void)
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{
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#ifndef CONFIG_IPQ5332_RUMI
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unsigned int reg_val;
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reg_val = readl(PLL_REFERENCE_CLOCK);
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@ -582,7 +566,6 @@ void cmbblk_init(void)
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reg_val |= BIT(6);
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writel(reg_val, PLL_POWER_ON_AND_RESET);
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mdelay(10);
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#endif
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}
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void eth_clock_init(void)
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@ -57,7 +57,6 @@ phy_info_t *swt_info[QCA8084_MAX_PORTS] = {0};
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ipq5332_edma_port_info_t *port_info[IPQ5332_PHY_MAX] = {0};
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int sgmii_mode[2] = {0};
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#ifndef CONFIG_IPQ5332_RUMI
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extern void ipq_phy_addr_fixup(void);
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extern void ipq_clock_init(void);
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extern int ipq_sw_mdio_init(const char *);
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@ -82,15 +81,12 @@ extern int ipq_qca8337_link_update(ipq_s17c_swt_cfg_t *s17c_swt_cfg);
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extern void ipq_s17c_switch_reset(int gpio);
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ipq_s17c_swt_cfg_t s17c_swt_cfg;
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#endif
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#endif
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static int tftp_acl_our_port;
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#ifndef CONFIG_IPQ5332_RUMI
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#ifdef CONFIG_QCA8084_SWT_MODE
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static int qca8084_swt_enb = 0;
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static int qca8084_chip_detect = 0;
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#endif
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#endif
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/*
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* EDMA hardware instance
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@ -885,7 +881,6 @@ static void ipq5332_edma_disable_intr(struct ipq5332_edma_hw *ehw)
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IPQ5332_EDMA_MASK_INT_DISABLE);
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}
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#ifndef CONFIG_IPQ5332_RUMI
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void print_eth_info(int mac_unit, int phy_id, char *status, int speed,
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char *duplex)
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{
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@ -893,14 +888,11 @@ void print_eth_info(int mac_unit, int phy_id, char *status, int speed,
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status, speed, duplex);
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}
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#endif
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static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
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{
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int i;
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u8 status = 0;
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int mac_speed = 0x1;
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#ifndef CONFIG_IPQ5332_RUMI
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struct ipq5332_eth_dev *priv = eth_dev->priv;
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struct phy_ops *phy_get_ops;
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static fal_port_speed_t old_speed[IPQ5332_PHY_MAX] =
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@ -914,14 +906,12 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
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int phy_addr = -1, ret = -1;
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phy_info_t *phy_info;
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int sgmii_mode = EPORT_WRAPPER_SGMII0_RGMII4, sfp_mode = -1;
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#endif
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/*
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* Check PHY link, speed, Duplex on all phys.
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* we will proceed even if single link is up
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* else we will return with -1;
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*/
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for (i = 0; i < IPQ5332_PHY_MAX; i++) {
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#ifndef CONFIG_IPQ5332_RUMI
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phy_info = port_info[i]->phy_info;
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if (phy_info->phy_type == UNUSED_PHY_TYPE)
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continue;
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@ -999,9 +989,6 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
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dp[duplex]);
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continue;
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}
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#endif
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#ifndef CONFIG_IPQ5332_RUMI
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/*
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* Note: If the current port link is up and its speed is
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* different from its initially configured speed, only then
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@ -1136,21 +1123,12 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
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}
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ipq5332_speed_clock_set(i, clk);
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#else
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ppe_port_bridge_txmac_set(i, 1);
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//FAL_SPEED_5000
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mac_speed = 0x5;
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ipq5332_uxsgmii_speed_set(i, mac_speed,
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FAL_DUPLEX_BUTT, status);
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#endif
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}
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#ifndef CONFIG_IPQ5332_RUMI
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if (linkup <= 0) {
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/* No PHY link is alive */
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return -1;
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}
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#endif
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pr_info("%s: done\n", __func__);
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@ -1711,7 +1689,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
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int i;
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int ret = -1;
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ipq5332_edma_board_cfg_t ledma_cfg, *edma_cfg;
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#ifndef CONFIG_IPQ5332_RUMI
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phy_info_t *phy_info;
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int phy_id;
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uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2;
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@ -1726,13 +1703,11 @@ int ipq5332_edma_init(void *edma_board_cfg)
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int s17c_swt_enb = 0, s17c_rst_gpio = 0;
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#endif
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int node, phy_addr, mode, phy_node = -1;
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#endif
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/*
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* Init non cache buffer
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*/
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noncached_init();
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#ifndef CONFIG_IPQ5332_RUMI
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node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
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#ifdef CONFIG_QCA8084_SWT_MODE
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qca8084_swt_enb = fdtdec_get_uint(gd->fdt_blob, node,
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@ -1785,7 +1760,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
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printf("Error:switch_mac_mode0 not specified in dts");
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return mode;
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}
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#endif
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memset(c_info, 0, (sizeof(c_info) * IPQ5332_EDMA_DEV));
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memset(enet_addr, 0, sizeof(enet_addr));
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@ -1862,7 +1836,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
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ipq5332_edma_dev[i]->c_info = c_info[i];
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ipq5332_edma_hw_addr = IPQ5332_EDMA_CFG_BASE;
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#ifndef CONFIG_IPQ5332_RUMI
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ret = ipq_sw_mdio_init(edma_cfg->phy_name);
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if (ret)
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goto init_failed;
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@ -1979,14 +1952,12 @@ int ipq5332_edma_init(void *edma_board_cfg)
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break;
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}
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}
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#endif
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ret = ipq5332_edma_hw_init(hw[i]);
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if (ret)
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goto init_failed;
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#ifndef CONFIG_IPQ5332_RUMI
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#ifdef CONFIG_QCA8084_SWT_MODE
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/** QCA8084 switch specific configurations */
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if (qca8084_swt_enb && qca8084_chip_detect) {
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@ -2020,7 +1991,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
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#ifdef CONFIG_ATHRS17C_SWITCH
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if (s17c_swt_cfg.chip_detect)
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ipq_qca8337_switch_init(&s17c_swt_cfg);
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#endif
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#endif
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eth_register(dev[i]);
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}
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@ -21,9 +21,7 @@
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#include <common.h>
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#include <asm/global_data.h>
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#include "ipq5332_ppe.h"
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#ifndef CONFIG_IPQ5332_RUMI
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#include "ipq5332_uniphy.h"
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#endif
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#include <fdtdec.h>
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#include "ipq_phy.h"
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@ -269,8 +267,6 @@ void ppe_mac_packet_filter_set(uint32_t port)
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(port * MAC_PACKET_FILTER_ADDRESS),
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0x80000081);
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}
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#ifndef CONFIG_IPQ5332_RUMI
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/*
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* ipq5332_port_mac_clock_reset()
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*/
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@ -374,7 +370,6 @@ void ipq5332_10g_r_speed_set(int port, int status)
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ppe_port_rxmac_status_set(port);
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ppe_mac_packet_filter_set(port);
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}
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#endif
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void ppe_xgmac_speed_set(uint32_t port, int speed)
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{
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@ -456,7 +451,6 @@ void ipq5332_xgmac_sgmiiplus_speed_set(int port, int speed, int status)
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void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
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int status)
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{
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#ifndef CONFIG_IPQ5332_RUMI
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uint32_t uniphy_index;
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if (port == PORT0)
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@ -466,12 +460,9 @@ void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
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ppe_uniphy_usxgmii_autoneg_completed(uniphy_index);
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ppe_uniphy_usxgmii_speed_set(uniphy_index, speed);
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#endif
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ppe_xgmac_speed_set(port, speed);
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#ifndef CONFIG_IPQ5332_RUMI
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ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex);
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ppe_uniphy_usxgmii_port_reset(uniphy_index);
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#endif
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ppe_port_bridge_txmac_set(port, status);
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ppe_port_txmac_status_set(port);
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ppe_port_rxmac_status_set(port);
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@ -516,7 +507,6 @@ static void ipq5332_ppe_flow_map_tbl_set(int queue, int port)
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*/
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static void ipq5332_ppe_tdm_configuration(void)
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{
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#ifndef CONFIG_IPQ5332_RUMI
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ipq5332_ppe_reg_write(0xc000, 0x22);
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ipq5332_ppe_reg_write(0xc010, 0x30);
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ipq5332_ppe_reg_write(0xc020, 0x21);
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@ -564,19 +554,6 @@ static void ipq5332_ppe_tdm_configuration(void)
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writel(0x303,(void *)0x3a026100);
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writel(0x303,(void *)0x3a026104);
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writel(0x303,(void *)0x3a026108);
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#else
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ipq5332_ppe_reg_write(0xc000, 0x20);
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ipq5332_ppe_reg_write(0xc010, 0x32);
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ipq5332_ppe_reg_write(0xc020, 0x21);
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ipq5332_ppe_reg_write(0xc030, 0x30);
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ipq5332_ppe_reg_write(0xc040, 0x22);
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ipq5332_ppe_reg_write(0xc050, 0x31);
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ipq5332_ppe_reg_write(0xb000, 0x80000006);
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ipq5332_ppe_reg_write(0x47a000, 0xfa10);
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ipq5332_ppe_reg_write(0x47a010, 0xfc21);
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ipq5332_ppe_reg_write(0x47a020, 0xf902);
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ipq5332_ppe_reg_write(0x400000, 0x3);
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#endif
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}
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/*
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@ -777,11 +754,8 @@ void ipq5332_ppe_interface_mode_init(void)
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return;
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}
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#ifndef CONFIG_IPQ5332_RUMI
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ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0);
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ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1);
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#endif
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/*
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* Port1 and Port2 can be used as GMAC or XGMAC.
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*/
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