The QPIC XFER STEPS will not be configured in non NAND boot
mode and the data transfer speed will be very slow. Now this
patch reads the timing parameter from ONFI page and configures
the NAND XFER STEPS registers for highest supported ONFI mode.
For NON ONFI device, it will configure to default mode.
Change-Id: I2daf4a92255307efc53db9bb7fe2f02e8c00c3fa
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Cleared dynamically allocated region for spi global data
to avoid garbage values causing data abort.
Change-Id: Ie278cb3a1374d347d7dfb20b59059dfbf9a7ae42
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
If the PCIE cards are not connected, executing the pci
commands lead to the crash.
Change-Id: Id68ab1a39bfc3319d17af2fe6a3c8d4c1af039b0
Signed-off-by: smuthayy <smuthayy@codeaurora.org>
ipq40xx, ipq807x hardware share the qca8075 phy. So the qca8075 phy
mdio, driver has been moved to common directory for use by both the
hardware.
Change-Id: Id6e9342438ffbdf8599860df6fbb39bba30429b3
Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
SPI-NOR flash option field was uninitialized which was
giving improper flash information during sf probe.
Initialized to zero during spi initialization.
Change-Id: I26df0a491e96071d598cc281c42e32408f34d29f
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
Added the ipq807x ethernet edma, ppe driver support
Change-Id: Ibcac04d8a60c1ca74549834b70735a6f15b58358
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
This patch enables qca_mmc driver and
also has the changes required for emmc
support
Change-Id: Icc8d807caffced79d6ca576fe6220c522ebda3f7
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
Added the ipq807x ethernet edma, ppe, gmac driver support
in the u-boot
Change-Id: I1d8ddd19f2c3d3765adda2253d3b71876142aa59
Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
As the U-boot source is going to be common between ARM and MIPS
architecture , it is required to pick only the files specific
to the respective architectures during the build.
So, move the qca arm target specific common files to another
sub level by specifying the ARCH arm.
Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
* changes:
ipq807x: Initialize TLV and CPU context dump size
ipq806x: Initialize TLV and CPU context dump size
ipq40xx: Added flash crashdump data support
This patch initialize TLV and CPU context dump size,
required for crashdump collection in flash.
Change-Id: I960300c3ea6c97481a7c5fd551b648454c13deef
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
This fix removes the mmc_init that is being called during
board init to prevent error message in cases where eMMC
card is not connected.
Change-Id: I918c71c391002d24e704be30043ff0cc8dfd4f83
Signed-off-by: G Dhivya <gdhivya@codeaurora.org>
This change initializes the CPU PLL , configures the
timer, DRAM & enables the serial console for the
AP152 target.
Change-Id: If2a6884813250c09a856c3cb2e1783bf3940619c
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
1. Added ethernet support for DB149
2. Added gmac_gpio node to aliases, to make
it common across the boards
Change-Id: I18a3d3ebaac993635830d36bd7c51f91ebd6749b
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
The writebufsize is introduced in mtd struct for the ubi fastmap
support.
This is not initialized in the qpic nand driver which leads to ubi
error.
Fixed the following ubi error.
bad write buffer size 0 for 2048 min. I/O unit
UBI init error 22
Change-Id: I35778366b95930bd01108bf300f073ee21940bc6
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
All properties of spi_slave as defined in spi.h
are initialised to avoid junk values.
Change-Id: I154bddccb12fe7e5c4787e870927610de85cda1c
Signed-off-by: Akila N <akilan@codeaurora.org>
