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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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ipq807x: Added the PCIE phy support
Change-Id: I30212d0b82a28c131ec35ec8eeada3b91f8369a1 Signed-off-by: smuthayy <smuthayy@codeaurora.org>
This commit is contained in:
smuthayy
Gerrit - the friendly Code Review server
parent
313a244c7e
commit
7c309ca403
2 changed files with 180 additions and 6 deletions
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@ -254,9 +254,10 @@
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0x20000f20 0xa8
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0x20300000 0xd00000
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0x20100000 0x100000
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0x01875004 0x40>;
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0x01875004 0x40
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0x86000 0x1000>;
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reg-names = "pci_dbi", "parf", "elbi", "axi_bars",
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"axi_conf", "pci_rst";
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"axi_conf", "pci_rst", "pci_phy";
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perst_gpio = <58>;
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pci_gpio {
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@ -284,9 +285,10 @@
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0x10000f20 0xa8
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0x10300000 0xd00000
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0x10100000 0x100000
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0x1876004 0x40>;
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0x1876004 0x40
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0x8E000 0x1000>;
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reg-names = "pci_dbi", "parf", "elbi", "axi_bars",
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"axi_conf", "pci_rst";
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"axi_conf", "pci_rst", "pci_phy";
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perst_gpio = <61>;
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pci_gpio {
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@ -90,8 +90,78 @@ DECLARE_GLOBAL_DATA_PTR;
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#define PCIE20_SIZE SZ_4K
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#define PCIE_AXI_CONF_SIZE SZ_1M
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#define PCIE_USB3_PCS_POWER_DOWN_CONTROL 0x804
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x34
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#define QSERDES_COM_CLK_ENABLE1 0x38
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#define QSERDES_COM_BG_TRIM 0x70
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#define QSERDES_COM_LOCK_CMP_EN 0xC8
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#define QSERDES_COM_VCO_TUNE_MAP 0x128
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#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
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#define QSERDES_COM_VCO_TUNE_TIMER2 0x144
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#define QSERDES_COM_CMN_CONFIG 0x194
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#define QSERDES_COM_PLL_IVCO 0x48
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#define QSERDES_COM_HSCLK_SEL 0x178
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#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19C
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#define QSERDES_COM_CORE_CLK_EN 0x18C
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#define QSERDES_COM_CORECLK_DIV 0x184
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#define QSERDES_COM_RESETSM_CNTRL 0xB4
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#define QSERDES_COM_BG_TIMER 0xC
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#define QSERDES_COM_SYSCLK_EN_SEL 0xAC
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#define QSERDES_COM_DEC_START_MODE0 0xD0
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#define QSERDES_COM_DIV_FRAC_START3_MODE0 0xE4
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#define QSERDES_COM_DIV_FRAC_START2_MODE0 0xE0
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#define QSERDES_COM_DIV_FRAC_START1_MODE0 0xDC
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#define QSERDES_COM_LOCK_CMP3_MODE0 0x54
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#define QSERDES_COM_LOCK_CMP2_MODE0 0x50
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#define QSERDES_COM_LOCK_CMP1_MODE0 0x4C
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#define QSERDES_COM_CLK_SELECT 0x174
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#define QSERDES_COM_SYS_CLK_CTRL 0x3C
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#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x40
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#define QSERDES_COM_CP_CTRL_MODE0 0x78
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#define QSERDES_COM_PLL_RCTRL_MODE0 0x84
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#define QSERDES_COM_PLL_CCTRL_MODE0 0x90
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#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10C
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#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
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#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0xA8
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#define QSERDES_COM_VCO_TUNE_CTRL 0xC
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#define QSERDES_COM_SSC_EN_CENTER 0x10
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#define QSERDES_COM_SSC_PER1 0x1C
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#define QSERDES_COM_SSC_PER2 0x20
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#define QSERDES_COM_SSC_ADJ_PER1 0x14
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#define QSERDES_COM_SSC_ADJ_PER2 0x18
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#define QSERDES_COM_SSC_STEP_SIZE1 0x24
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#define QSERDES_COM_SSC_STEP_SIZE2 0x28
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#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x268
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#define QSERDES_TX_LANE_MODE 0x294
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#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x254
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#define QSERDES_TX_RCV_DETECT_LVL_2 0x2AC
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#define QSERDES_RX_SIGDET_ENABLES 0x510
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#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x51C
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x4D8
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4DC
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x4E0
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#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x448
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#define QSERDES_RX_UCDR_SO_GAIN 0x41C
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#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x410
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#define QSERDES_COM_CLK_EP_DIV 0x74
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#define PCIE_USB3_PCS_ENDPOINT_REFCLK_DRIVE 0x854
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#define PCIE_USB3_PCS_OSC_DTCT_ACTIONS 0x9AC
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#define PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x8A0
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#define PCIE_USB3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x9E0
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#define PCIE_USB3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x9DC
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#define PCIE_USB3_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x9A8
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#define PCIE_USB3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x8A4
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#define PCIE_USB3_PCS_PLL_LOCK_CHK_DLY_TIME 0x8A8
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#define QSERDES_RX_SIGDET_CNTRL 0x514
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#define PCIE_USB3_PCS_RX_SIGDET_LVL 0x9D8
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#define PCIE_USB3_PCS_TXDEEMPH_M6DB_V0 0x824
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#define PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0 0x828
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#define PCIE_USB3_PCS_SW_RESET 0x800
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#define PCIE_USB3_PCS_START_CONTROL 0x808
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static unsigned int local_buses[] = { 0, 0 };
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struct pci_controller pci_hose[PCI_MAX_DEVICES];
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static int phy_initialised;
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enum pcie_verion{
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PCIE_V0,
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@ -106,6 +176,10 @@ static const struct udevice_id pcie_ver_ids[] = {
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{ },
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};
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struct phy_regs {
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u32 reg_offset;
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u32 val;
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};
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struct ipq_pcie {
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struct pci_controller hose;
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@ -115,6 +189,7 @@ struct ipq_pcie {
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struct fdt_resource axi_conf;
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struct fdt_resource axi_bars;
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struct fdt_resource pci_rst;
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struct fdt_resource pci_phy;
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int rst_gpio;
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int linkup;
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@ -328,8 +403,11 @@ void pcie_linkup(struct ipq_pcie *pcie)
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{
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int j, val;
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writel(SLV_ADDR_SPACE_SZ, pcie->parf.start + PARF_SLV_ADDR_SPACE_SIZE);
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mdelay(100);
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if (pcie->version != PCIE_V2)
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{
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writel(SLV_ADDR_SPACE_SZ, pcie->parf.start + PARF_SLV_ADDR_SPACE_SIZE);
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mdelay(100);
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}
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writel(0x0, pcie->pci_dbi.start + PCIE_0_PORT_FORCE_REG);
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val = (L1_ENTRANCE_LATENCY(3) |
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@ -433,6 +511,12 @@ static int ipq_pcie_parse_dt(const void *fdt, int id,
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return err;
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}
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err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pci_phy",
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&pcie->pci_phy);
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if (err < 0) {
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error("resource \"cs\" not found");
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return err;
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}
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rst_gpio = fdtdec_get_int(fdt, node, "perst_gpio", 0);
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if (rst_gpio <= 0) {
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debug("PCI: Can't get perst_gpio\n");
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@ -522,6 +606,93 @@ void pci_controller_init_v1(struct ipq_pcie *pcie)
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writel(val, pcie->pci_rst.start);
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}
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static const struct phy_regs pcie_phy_regs[] = {
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{ PCIE_USB3_PCS_POWER_DOWN_CONTROL, 0x00000003 },
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{ QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x00000018 },
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{ QSERDES_COM_CLK_ENABLE1, 0x00000010 },
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{ QSERDES_COM_BG_TRIM, 0x0000000f },
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{ QSERDES_COM_LOCK_CMP_EN, 0x00000001 },
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{ QSERDES_COM_VCO_TUNE_MAP, 0x00000000 },
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{ QSERDES_COM_VCO_TUNE_TIMER1, 0x000000ff },
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{ QSERDES_COM_VCO_TUNE_TIMER2, 0x0000001f },
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{ QSERDES_COM_CMN_CONFIG, 0x00000006 },
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{ QSERDES_COM_PLL_IVCO, 0x0000000f },
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{ QSERDES_COM_HSCLK_SEL, 0x00000000 },
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{ QSERDES_COM_SVS_MODE_CLK_SEL, 0x00000001 },
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{ QSERDES_COM_CORE_CLK_EN, 0x00000020 },
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{ QSERDES_COM_CORECLK_DIV, 0x0000000a },
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{ QSERDES_COM_RESETSM_CNTRL, 0x00000020 },
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{ QSERDES_COM_BG_TIMER, 0x00000009 },
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{ QSERDES_COM_SYSCLK_EN_SEL, 0x0000000a },
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{ QSERDES_COM_DEC_START_MODE0, 0x00000082 },
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{ QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00000003 },
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{ QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00000055 },
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{ QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00000055 },
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{ QSERDES_COM_LOCK_CMP3_MODE0, 0x00000000 },
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{ QSERDES_COM_LOCK_CMP2_MODE0, 0x0000000D },
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{ QSERDES_COM_LOCK_CMP1_MODE0, 0x00000D04 },
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{ QSERDES_COM_CLK_SELECT, 0x00000033 },
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{ QSERDES_COM_SYS_CLK_CTRL, 0x00000002 },
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{ QSERDES_COM_SYSCLK_BUF_ENABLE, 0x0000001f },
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{ QSERDES_COM_CP_CTRL_MODE0, 0x0000000b },
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{ QSERDES_COM_PLL_RCTRL_MODE0, 0x00000016 },
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{ QSERDES_COM_PLL_CCTRL_MODE0, 0x00000028 },
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{ QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00000000 },
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{ QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x00000080 },
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{ QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x00000001 },
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{ QSERDES_COM_VCO_TUNE_CTRL, 0x0000000a },
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{ QSERDES_COM_SSC_EN_CENTER, 0x00000001 },
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{ QSERDES_COM_SSC_PER1, 0x00000031 },
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{ QSERDES_COM_SSC_PER2, 0x00000001 },
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{ QSERDES_COM_SSC_ADJ_PER1, 0x00000002 },
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{ QSERDES_COM_SSC_ADJ_PER2, 0x00000000 },
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{ QSERDES_COM_SSC_STEP_SIZE1, 0x0000002f },
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{ QSERDES_COM_SSC_STEP_SIZE2, 0x00000019 },
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{ QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x00000045 },
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{ QSERDES_TX_LANE_MODE, 0x00000006 },
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{ QSERDES_TX_RES_CODE_LANE_OFFSET, 0x00000002 },
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{ QSERDES_TX_RCV_DETECT_LVL_2, 0x00000012 },
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{ QSERDES_RX_SIGDET_ENABLES, 0x0000001c },
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{ QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x00000014 },
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{ QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00000001 },
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{ QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00000000 },
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{ QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x000000db },
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{ QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x0000004b },
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{ QSERDES_RX_UCDR_SO_GAIN, 0x00000004 },
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{ QSERDES_RX_UCDR_SO_GAIN_HALF, 0x00000004 },
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{ QSERDES_COM_CLK_EP_DIV, 0x00000019 },
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{ PCIE_USB3_PCS_ENDPOINT_REFCLK_DRIVE, 0x00000004 },
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{ PCIE_USB3_PCS_OSC_DTCT_ACTIONS, 0x00000000 },
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{ PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00000040 },
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{ PCIE_USB3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00000000 },
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{ PCIE_USB3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x00000040 },
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{ PCIE_USB3_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x00000000 },
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{ PCIE_USB3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x00000040 },
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{ PCIE_USB3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x00000073 },
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{ QSERDES_RX_SIGDET_CNTRL, 0x00000007 },
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{ PCIE_USB3_PCS_RX_SIGDET_LVL, 0x00000099 },
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{ PCIE_USB3_PCS_TXDEEMPH_M6DB_V0, 0x00000015 },
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{ PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0, 0x0000000e },
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{ PCIE_USB3_PCS_SW_RESET, 0x00000000 },
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{ PCIE_USB3_PCS_START_CONTROL, 0x00000003 },
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};
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void pcie_phy_init(struct ipq_pcie *pcie)
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{
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int i;
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const struct phy_regs *regs = pcie_phy_regs;
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if (!phy_initialised) {
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writel(0x10000000, pcie->parf.start + 0x358);
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writel(0x10000000, pcie->parf.start + 0x8358);
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mdelay(100);
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phy_initialised = 1;
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}
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for (i = 0; i < ARRAY_SIZE(pcie_phy_regs); i++)
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writel(regs[i].val, pcie->pci_phy.start + regs[i].reg_offset);
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}
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static int pci_ipq_ofdata_to_platdata(int id, struct ipq_pcie *pcie)
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{
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@ -535,6 +706,7 @@ static int pci_ipq_ofdata_to_platdata(int id, struct ipq_pcie *pcie)
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pcie_linkup(pcie);
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break;
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case PCIE_V2:
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pcie_phy_init(pcie);
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pcie_linkup(pcie);
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break;
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default:
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