mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-02 15:33:55 +01:00
ipq807x: Deinit pcie before loading kernel
Change-Id: I22fe87dac2fd8f55978481fae71ee65281dfd204 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This commit is contained in:
parent
86f7fe94c9
commit
6f1452c953
5 changed files with 88 additions and 0 deletions
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@ -52,6 +52,7 @@ void gpio_set_value(unsigned int gpio, unsigned int out);
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int gpio_get_value(unsigned int gpio);
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int qca_gpio_init(int offset);
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int qca_gpio_deinit(int offset);
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/* GPIO TLMM: Output value */
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#define GPIO_OUT_LOW 0
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@ -480,6 +480,8 @@ static int do_boot_signedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const a
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board_mmc_deinit();
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#endif
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board_pci_deinit();
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ret = config_select(request, runcmd, sizeof(runcmd));
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if (debug)
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@ -611,6 +613,8 @@ static int do_boot_unsignedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const
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dcache_enable();
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board_pci_deinit();
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setenv("mtdids", mtdids);
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ret = genimg_get_format((void *)CONFIG_SYS_LOAD_ADDR);
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@ -304,6 +304,33 @@ static void pcie_clock_init(int id)
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}
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}
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static void pcie_clock_deinit(int id)
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{
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if (id == 0) {
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writel(0x0, GCC_PCIE0_AUX_CMD_RCGR);
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writel(0x0, GCC_PCIE0_AXI_CFG_RCGR);
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writel(0x0, GCC_PCIE0_AXI_CMD_RCGR);
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mdelay(100);
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writel(0x0, GCC_SYS_NOC_PCIE0_AXI_CLK);
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writel(0x0, GCC_PCIE0_AHB_CBCR);
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writel(0x0, GCC_PCIE0_AXI_M_CBCR);
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writel(0x0, GCC_PCIE0_AXI_S_CBCR);
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writel(0x0, GCC_PCIE0_AUX_CBCR);
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writel(0x0, GCC_PCIE0_PIPE_CBCR);
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writel(0x0, GCC_PCIE1_AUX_CMD_RCGR);
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writel(0x0, GCC_PCIE1_AXI_CFG_RCGR);
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writel(0x0, GCC_PCIE1_AXI_CMD_RCGR);
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mdelay(100);
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writel(0x0, GCC_SYS_NOC_PCIE1_AXI_CLK);
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writel(0x0, GCC_PCIE1_AHB_CBCR);
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writel(0x0, GCC_PCIE1_AXI_M_CBCR);
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writel(0x0, GCC_PCIE1_AXI_S_CBCR);
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writel(0x0, GCC_PCIE1_AUX_CBCR);
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writel(0x0, GCC_PCIE1_PIPE_CBCR);
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}
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}
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void board_pci_init(int id)
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{
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int node, gpio_node;
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@ -323,6 +350,38 @@ void board_pci_init(int id)
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return ;
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}
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void board_pci_deinit()
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{
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int node, gpio_node, i, err;
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char name[16];
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struct fdt_resource parf;
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struct fdt_resource pci_phy;
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for (i = 0; i < PCI_MAX_DEVICES; i++) {
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sprintf(name, "pci%d", i);
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node = fdt_path_offset(gd->fdt_blob, name);
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if (node < 0) {
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printf("Could not find PCI in device tree\n");
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return;
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}
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err = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", "parf",
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&parf);
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writel(0x0, parf.start + 0x358);
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writel(0x1, parf.start + 0x40);
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err = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", "pci_phy",
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&pci_phy);
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writel(0x1, pci_phy.start + 800);
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writel(0x0, pci_phy.start + 804);
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gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "pci_gpio");
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if (gpio_node >= 0)
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qca_gpio_deinit(gpio_node);
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}
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pcie_clock_deinit(0);
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return ;
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}
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int ipq_fdt_fixup_socinfo(void *blob)
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{
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return 0;
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@ -30,6 +30,9 @@
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#define GCC_SDCC1_APPS_D 0x1842014
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#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c
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#define GCC_SYS_NOC_PCIE0_AXI_CLK 0x01826048
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#define GCC_PCIE0_PHY_BCR 0x01875038
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#define GCC_PCIE0PHY_PHY_BCR 0x0187503C
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#define GCC_PCIE0_AXI_M_CBCR 0x01875008
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#define GCC_PCIE0_AXI_S_CBCR 0x0187500C
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#define GCC_PCIE0_AHB_CBCR 0x01875010
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@ -39,6 +42,9 @@
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#define GCC_PCIE0_AXI_CMD_RCGR 0x01875050
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#define GCC_PCIE0_AXI_CFG_RCGR 0x01875058
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#define GCC_SYS_NOC_PCIE1_AXI_CLK 0x0182604C
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#define GCC_PCIE1_PHY_BCR 0x01876038
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#define GCC_PCIE1PHY_PHY_BCR 0x0187603C
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#define GCC_PCIE1_AXI_M_CBCR 0x01876008
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#define GCC_PCIE1_AXI_S_CBCR 0x0187600C
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#define GCC_PCIE1_AHB_CBCR 0x01876010
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@ -103,3 +103,21 @@ int qca_gpio_init(int offset)
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}
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return 0;
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}
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int qca_gpio_deinit(int offset)
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{
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struct qca_gpio_config gpio_config;
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for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0;
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offset = fdt_next_subnode(gd->fdt_blob, offset)) {
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gpio_config.gpio = fdtdec_get_uint(gd->fdt_blob,
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offset, "gpio", 0);
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unsigned int *addr =
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(unsigned int *)GPIO_CONFIG_ADDR(gpio_config.gpio);
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writel(1, addr);
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addr = (unsigned int *)GPIO_IN_OUT_ADDR(gpio_config.gpio);
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writel(1, addr);
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}
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return 0;
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}
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