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ARM: qup_spi: Enabled bam support for spi-nor

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Change-Id: I7bf9335ed5c0e6a439c5a4169319f1d422e1ae7d
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Gopinath Sekar <gsekar@codeaurora.org>
This commit is contained in:
Gokul Sriram Palanisamy 2017-06-07 22:16:31 +05:30
parent f5993e4346
commit 3a93d3ccb9
4 changed files with 18 additions and 105 deletions
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2
drivers/spi/Makefile
View file

@ -34,7 +34,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
obj-$(CONFIG_ICH_SPI) += ich.o
ifdef CONFIG_QCA_SPI
obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi.o
obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi.o
obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi_bam.o
obj-$(CONFIG_ARCH_IPQ806x) += ipq_spi.o
endif
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o

77
drivers/spi/qca_qup_spi_bam.c
View file

@ -1,6 +1,6 @@
/*
* BLSP QUP SPI controller driver.
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@ -29,36 +29,13 @@
*/
#include <common.h>
#include <watchdog.h>
#include <spi.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch-qcom-common/gpio.h>
#include <asm/arch-qcom-common/bam.h>
#include <asm/arch-ipq40xx/iomap.h>
#include <asm/arch-qca-common/bam.h>
#include "qca_qup_spi_bam.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* CS GPIO number array cs_gpio_array[port_num][cs_num]
* cs_gpio_array[0][x] -- QUP0
*/
static unsigned int cs_gpio_array_dk01[NUM_PORTS][NUM_CS] = {
{
QUP0_SPI_CS_0, QUP0_SPI_CS_1_DK01,
},
};
static unsigned int cs_gpio_array_dk04[NUM_PORTS][NUM_CS] = {
{
QUP0_SPI_CS_0, QUP0_SPI_CS_1_DK04,
},
};
static unsigned int (*cs_gpio_array)[NUM_CS] = cs_gpio_array_dk01;
static int check_bit_state(uint32_t reg_addr, int bit_num, int val,
int us_delay)
{
@ -184,30 +161,6 @@ void spi_init()
/* do nothing */
}
/*
* Function to assert and De-assert chip select
*/
static void CS_change(int port_num, int cs_num, int enable)
{
unsigned int cs_gpio = cs_gpio_array[port_num][cs_num];
uint32_t addr = GPIO_IN_OUT_ADDR(cs_gpio);
uint32_t val = readl(addr);
val &= ~(GPIO_OUT);
if (!enable)
val |= GPIO_OUT;
writel(val, addr);
}
static void blsp_pin_config(unsigned int port_num, int cs_num)
{
unsigned int gpio;
gpio = cs_gpio_array[port_num][cs_num];
/* configure CS */
gpio_tlmm_config(gpio, FUNC_SEL_GPIO, GPIO_OUTPUT, GPIO_PULL_UP,
GPIO_DRV_STR_10MA, GPIO_FUNC_ENABLE, 0, 0, 0);
}
int qup_bam_init(struct ipq_spi_slave *ds)
{
unsigned int read_pipe = QUP0_DATA_PRODUCER_PIPE;
@ -296,9 +249,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
* controller will indefinitely wait for response from slave.
* Hence, return NULL.
*/
if (gd->bd->bi_arch_number == MACH_TYPE_IPQ40XX_AP_DK07_1_C2)
return NULL;
ds = malloc(sizeof(struct ipq_spi_slave));
if (!ds) {
printf("SPI error: malloc of SPI structure failed\n");
@ -339,14 +289,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
/* DMA mode */
ds->use_dma = CONFIG_QUP_SPI_USE_DMA;
if (ds->slave.cs == CONFIG_SF_SPI_NAND_CS) {
/* GPIO Configuration for SPI port */
if (gd->bd->bi_arch_number == MACH_TYPE_IPQ40XX_AP_DK04_1_C5)
cs_gpio_array = cs_gpio_array_dk04;
blsp_pin_config(ds->slave.bus, ds->slave.cs);
CS_change(ds->slave.bus, ds->slave.cs, CS_DEASSERT);
}
return &ds->slave;
err:
free(ds);
@ -940,12 +882,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return ret;
}
if (ds->slave.cs == CONFIG_SF_SPI_NAND_CS) {
setbits_le32(ds->regs->io_control, CS_POLARITY_MASK);
CS_change(ds->slave.bus, ds->slave.cs, CS_ASSERT);
} else {
write_force_cs(slave, 1);
}
write_force_cs(slave, 1);
}
if (dout != NULL) {
@ -961,13 +898,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
}
if (flags & SPI_XFER_END) {
/* To handle only when chip select change is needed */
if (ds->slave.cs == CONFIG_SF_SPI_NAND_CS) {
clrbits_le32(ds->regs->io_control, CS_POLARITY_MASK);
CS_change(ds->slave.bus, ds->slave.cs, CS_DEASSERT);
} else {
write_force_cs(slave, 0);
}
write_force_cs(slave, 0);
}
return ret;

43
drivers/spi/qca_qup_spi_bam.h
View file

@ -1,6 +1,6 @@
/*
* Register definitions for the IPQ40XX QUP-SPI Controller
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@ -28,8 +28,8 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _IPQ40XX_SPI_H_
#define _IPQ40XX_SPI_H_
#ifndef _IPQ_SPI_BAM_H_
#define _IPQ_SPI_BAM_H_
#define QUP0_BASE 0x78b5000
#define QUP1_BASE 0x78b6000
@ -70,8 +70,8 @@
#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008)
#define BLSP1_QUP_IO_MODES_REG (BLSP1_QUP_REG_BASE + 0x00000008)
#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
#define BLSP1_QUP_STATE_REG (BLSP1_QUP_REG_BASE + 0x00000004)
#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
#define BLSP1_QUP_STATE_REG (BLSP1_QUP_REG_BASE + 0x00000004)
#define BLSP0_QUP_INPUT_FIFOc_REG(c) \
@ -90,14 +90,14 @@
#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100)
#define BLSP1_QUP_MX_OUTPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000100)
#define BLSP0_QUP_MX_READ_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000208)
#define BLSP1_QUP_MX_READ_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000208)
#define BLSP0_QUP_MX_READ_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000208)
#define BLSP1_QUP_MX_READ_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000208)
#define BLSP0_QUP_MX_WRITE_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000150)
#define BLSP1_QUP_MX_WRITE_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000150)
#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
#define BLSP1_QUP_SW_RESET_REG (BLSP1_QUP_REG_BASE + 0x0000000c)
#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
#define BLSP1_QUP_SW_RESET_REG (BLSP1_QUP_REG_BASE + 0x0000000c)
#define QUP_STATE_VALID_BIT 2
#define QUP_STATE_VALID 1
@ -121,7 +121,6 @@
#define SLAVE_OPERATION (0 << 5)
#define CLK_ALWAYS_ON (0 << 9)
#define MX_CS_MODE (1 << 8)
#define CS_POLARITY_MASK (1 << 4)
#define NO_TRI_STATE (1 << 0)
#define FORCE_CS_MSK (1 << 11)
#define FORCE_CS_EN (1 << 11)
@ -268,8 +267,8 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
#define DATA_PRODUCER_PIPE_INDEX 1
/* QUP0 BAM pipe numbers */
#define QUP0_DATA_CONSUMER_PIPE 4
#define QUP0_DATA_PRODUCER_PIPE 5
#define QUP0_DATA_CONSUMER_PIPE 12
#define QUP0_DATA_PRODUCER_PIPE 13
/* QUP1 BAM pipe numbers */
#define QUP1_DATA_CONSUMER_PIPE 6
@ -297,23 +296,5 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
static struct bam_instance bam;
struct bam_desc qup_spi_data_desc_fifo[QUP_BAM_DATA_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE)));
#define min_t(type, x, y) \
({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
#define NUM_PORTS 1
#define NUM_CS 2
#define FUNC_SEL_GPIO 0
#define GPIO_DRV_STR_10MA 0x4
#define FUNC_SEL_GPIO 0
#define GPIO_FUNC_ENABLE 1
/* QUP0 CS GPIO mapping*/
#define QUP0_SPI_CS_0 54
#define QUP0_SPI_CS_1_DK01 59
#define QUP0_SPI_CS_1_DK04 45
#define CS_ASSERT 1
#define CS_DEASSERT 0
#endif /* _IPQ40XX_SPI_H_ */
#endif /* _IPQ_SPI_BAM_H_ */

1
include/configs/ipq807x.h
View file

@ -178,6 +178,7 @@ extern loff_t board_env_offset;
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
#define QCA_SPI_NOR_DEVICE "spi0.0"
#define CONFIG_QUP_SPI_USE_DMA 1
#define CONFIG_SCM_TZ64 1
/*