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ipq806x: Enabled SDCC support

Browse source 
This patch enables qca_mmc driver and
also has the changes required for emmc
support

Change-Id: Icc8d807caffced79d6ca576fe6220c522ebda3f7
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
This commit is contained in:
Vasudevan Murugesan 2017-01-30 19:17:04 +05:30 • committed by Gerrit - the friendly Code Review server
parent f71a48c2df
commit f96d461a27
7 changed files with 136 additions and 15 deletions
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1
arch/arm/dts/ipq806x-ap145.dts
View file

@ -23,6 +23,7 @@
console = "/serial@16340000";
nand = "/nand@1A600000";
gmac_gpio = "/gmac1_gpio";
sdcc = "/sdcc@12400000";
};
serial@16340000 {

81
arch/arm/dts/ipq806x-soc.dtsi
View file

@ -459,4 +459,85 @@
};
};
sdcc@12400000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,sdcc";
reg = <0x12400000 0x2000>;
status = "ok";
emmc_gpio {
gpio38 {
gpio = <38>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio39 {
gpio = <39>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio40 {
gpio = <40>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio41 {
gpio = <41>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio42 {
gpio = <42>;
func = <2>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_16MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio43 {
gpio = <43>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio44 {
gpio = <44>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio45 {
gpio = <45>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio46 {
gpio = <46>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio47 {
gpio = <47>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_10MA>;
oe = <GPIO_OE_DISABLE>;
};
};
};
};

13
arch/arm/include/asm/arch-ipq806x/clk.h
View file

@ -33,6 +33,12 @@
#define Uart_clk_ns_mask (BM(31, 16) | BM(6, 0))
#define Uart_en_mask BIT(11)
#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
/* MD Registers */
#define MD4(m_lsb, m, n_lsb, n) \
(BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
#define MD8(m_lsb, m, n_lsb, n) \
(BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
/* NS Registers */
#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
@ -60,6 +66,13 @@
#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
#define SDC1_HCLK_CTL REG(0x2820)
#define SDC1_APPS_CLK_MD REG(0x2828)
#define SDC1_APPS_CLK_NS REG(0x282C)
#define SDC1_RESET REG(0x2830)
#define emmc_clk_ns_mask (BM(BIT_POS_23, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0))
#define emmc_en_mask BIT(11)
void i2c_clock_config(void);

8
board/qca/arm/common/cmd_bootqca.c
View file

@ -40,6 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
static qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
int ipq_fs_on_nand ;
extern int nand_env_device;
extern qca_mmc mmc_host;
#ifdef CONFIG_QCA_MMC
static qca_mmc *host = &mmc_host;
@ -451,16 +452,15 @@ static int do_boot_signedimg(cmd_tbl_t *cmdtp, int flag, int argc, char *const a
}
dcache_enable();
#ifdef CONFIG_QCA_MMC
board_mmc_deinit();
#endif
ret = config_select(request, runcmd, sizeof(runcmd));
if (debug)
printf(runcmd);
#ifdef CONFIG_QCA_MMC
board_mmc_deinit();
#endif
if (ret < 0 || run_command(runcmd, 0) != CMD_RET_SUCCESS) {
#ifdef CONFIG_QCA_MMC
mmc_initialize(gd->bd);

44
board/qca/arm/ipq806x/ipq806x.c
View file

@ -14,6 +14,7 @@
#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm-generic/errno.h>
#include <environment.h>
#include <fdtdec.h>
#include <asm/arch-qca-common/gsbi.h>
@ -92,20 +93,38 @@ void reset_cpu(unsigned long a)
while(1);
}
void emmc_clock_config(int mode)
{
/* TODO: To be filled */
}
int board_mmc_init(bd_t *bis)
{
int ret;
int node, gpio_node;
int ret = -ENODEV;
u32 *emmc_base;
int len;
mmc_host.base = MSM_SDC1_BASE;
mmc_host.clk_mode = MMC_IDENTIFY_MODE;
emmc_clock_config(mmc_host.clk_mode);
node = fdt_path_offset(gd->fdt_blob, "sdcc");
ret = qca_mmc_init(bis, &mmc_host);
if (node < 0) {
printf("SDCC : Node Not found, skipping initialization\n");
goto out;
}
emmc_base = fdt_getprop(gd->fdt_blob, node, "reg", &len);
if (emmc_base == FDT_ADDR_T_NONE) {
printf("No valid SDCC base address found in device tree\n");
goto out;
}
gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "emmc_gpio");
if (gpio_node >= 0) {
mmc_host.clk_mode = MMC_IDENTIFY_MODE;
mmc_host.base = fdt32_to_cpu(emmc_base[0]);
emmc_clock_config(mmc_host.clk_mode);
qca_gpio_init(gpio_node);
ret = qca_mmc_init(bis, &mmc_host);
}
out:
return ret;
}
void board_nand_init(void)
@ -306,3 +325,10 @@ int ipq_fdt_fixup_socinfo(void *blob)
printf("%s: cannot set cpu type %d\n", __func__, ret);
return ret;
}
void board_mmc_deinit(void)
{
emmc_clock_reset();
emmc_clock_disable();
}

2
drivers/mmc/Makefile
View file

@ -42,7 +42,7 @@ obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
obj-$(CONFIG_SDHCI_QCA) += qca_mmc.o
obj-$(CONFIG_QCA_MMC) += qca_mmc.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o

2
include/configs/ipq806x.h
View file

@ -151,7 +151,7 @@
/*
* MMC Configs
*/
#undef CONFIG_QCA_MMC
#define CONFIG_QCA_MMC
#ifdef CONFIG_QCA_MMC
#define CONFIG_CMD_MMC