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ipq807x: enable net, qca8075 phy reset and link detection code

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Change-Id: I978f5a16da7ecf56f006e0e7757a52c7d31b22cf
Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
This commit is contained in:
Jaiganesh Narayanan 2017-05-29 00:18:46 +05:30 • committed by Gerrit - the friendly Code Review server
parent 428fc1d379
commit 6fe9db26ac
7 changed files with 128 additions and 45 deletions
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17
board/qca/arm/ipq807x/ipq807x.c
View file

@ -130,18 +130,23 @@ void board_mmc_deinit(void)
int board_eth_init(bd_t *bis)
{
int ret;
int ret=0;
int tlmm_base = 0x1025000;
ipq807x_register_switch(ipq_qca8075_phy_init);
/* bring phy out of reset */
writel(0x203, tlmm_base);
writel(0, tlmm_base + 0x4);
writel(2, tlmm_base + 0x4);
writel(7, tlmm_base + 0x1f000);
writel(7, tlmm_base + 0x20000);
ret = ipq807x_edma_init(NULL);
if (ret != 0)
printf("%s: ipq807x_edma_init failed : %d\n", __func__, ret);
/* 8075 out of reset */
mdelay(100);
gpio_set_value(37, 1);
ipq807x_register_switch(ipq_qca8075_phy_init);
return ret;
}

2
common/board_r.c
View file

@ -917,7 +917,7 @@ init_fnc_t init_sequence_r[] = {
#endif
#ifdef CONFIG_CMD_NET
INIT_FUNC_WATCHDOG_RESET
//initr_net,
initr_net,
#endif
#ifdef CONFIG_POST
initr_post,

82
drivers/net/ipq807x/ipq807x_edma.c
View file

@ -35,7 +35,9 @@
#define pr_info(fmt, args...) printf(fmt, ##args);
#define pr_warn(fmt, args...) printf(fmt, ##args);
#ifndef CONFIG_IPQ807X_BRIDGED_MODE
#define IPQ807X_EDMA_MAC_PORT_NO 3
#endif
static struct ipq807x_eth_dev *ipq807x_edma_dev[IPQ807X_EDMA_DEV];
@ -46,6 +48,7 @@ extern void qca8075_ess_reset(void);
extern void psgmii_self_test(void);
extern void clear_self_test_config(void);
extern int ipq_sw_mdio_init(const char *);
extern void ipq_qca8075_dump_phy_regs(u32);
void ipq807x_register_switch(int(*sw_init)(struct phy_ops **ops))
{
@ -257,7 +260,7 @@ uint32_t ipq807x_edma_clean_tx(struct ipq807x_edma_hw *ehw,
* ipq807x_edma_clean_rx()
* Reap Rx descriptors
*/
static uint32_t ipq807x_edma_clean_rx(struct ipq807x_edma_common_info *c_info,
uint32_t ipq807x_edma_clean_rx(struct ipq807x_edma_common_info *c_info,
struct ipq807x_edma_rxdesc_ring *rxdesc_ring)
{
void *skb;
@ -858,6 +861,57 @@ static int ipq807x_eth_init(struct eth_device *eth_dev, bd_t *this)
struct ipq807x_edma_hw *ehw = &c_info->hw;
int i;
uint32_t data;
u8 status;
struct phy_ops *phy_get_ops;
fal_port_speed_t speed;
fal_port_duplex_t duplex;
char *lstatus[] = {"up", "Down"};
char *dp[] = {"Half", "Full"};
int linkup=0;
if (!priv->ops) {
printf ("Phy ops not mapped\n");
return -1;
}
phy_get_ops = priv->ops;
if (!phy_get_ops->phy_get_link_status ||
!phy_get_ops->phy_get_speed ||
!phy_get_ops->phy_get_duplex) {
printf ("Link status/Get speed/Get duplex not mapped\n");
return -1;
}
/*
* Check PHY link, speed, Duplex on all phys.
* we will proceed even if single link is up
* else we will return with -1;
*/
for (i = 0; i < PHY_MAX; i++) {
status = phy_get_ops->phy_get_link_status(priv->mac_unit, i);
if (status == 0)
linkup++;
phy_get_ops->phy_get_speed(priv->mac_unit, i, &speed);
phy_get_ops->phy_get_duplex(priv->mac_unit, i, &duplex);
switch (speed) {
case FAL_SPEED_10:
case FAL_SPEED_100:
case FAL_SPEED_1000:
printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
priv->mac_unit, i, lstatus[status], speed,
dp[duplex]);
break;
default:
printf("Unknown speed\n");
break;
}
}
if (linkup <= 0) {
/* No PHY link is alive */
return -1;
}
/*
* Alloc Rx buffers
@ -1474,6 +1528,7 @@ int ipq807x_edma_init(void *edma_board_cfg)
memset(enet_addr, 0, sizeof(enet_addr));
memset(&ledma_cfg, 0, sizeof(ledma_cfg));
edma_cfg = &ledma_cfg;
strcpy(edma_cfg->phy_name, "IPQ MDIO0");
/* Getting the MAC address from ART partition */
/* ret = get_eth_mac_address(enet_addr, IPQ807X_EDMA_DEV); */
@ -1548,24 +1603,6 @@ int ipq807x_edma_init(void *edma_board_cfg)
if (ret)
goto init_failed;
switch (edma_cfg->phy) {
case PHY_INTERFACE_MODE_PSGMII:
writel(PSGMIIPHY_PLL_VCO_VAL,
PSGMIIPHY_PLL_VCO_RELATED_CTRL);
writel(PSGMIIPHY_VCO_VAL,
PSGMIIPHY_VCO_CALIBRATION_CTRL);
/* wait for 10ms */
mdelay(10);
writel(PSGMIIPHY_VCO_RST_VAL, PSGMIIPHY_VCO_CALIBRATION_CTRL);
break;
case PHY_INTERFACE_MODE_RGMII:
writel(0x1, RGMII_TCSR_ESS_CFG);
writel(0x400, ESS_RGMII_CTRL);
break;
default:
printf("unknown MII interface\n");
goto init_failed;
}
if (!sw_init_done) {
if (ipq807x_switch_init(&ipq807x_edma_dev[i]->ops) == 0) {
@ -1576,13 +1613,6 @@ int ipq807x_edma_init(void *edma_board_cfg)
}
}
if(edma_cfg->phy == PHY_INTERFACE_MODE_PSGMII) {
qca8075_ess_reset();
mdelay(100);
psgmii_self_test();
mdelay(300);
clear_self_test_config();
}
ret = ipq807x_edma_hw_init(hw[i]);
if (ret)

2
drivers/net/ipq807x/ipq807x_edma.h
View file

@ -302,7 +302,7 @@ typedef struct {
uint mac_conn_to_phy;
phy_interface_t phy;
ipq807x_edma_phy_addr_t phy_addr;
const char phy_name[MDIO_NAME_LEN];
char phy_name[MDIO_NAME_LEN];
} ipq807x_edma_board_cfg_t;
extern void ipq807x_ppe_provision_init(void);

53
drivers/net/ipq_common/ipq_qca8075.c
View file

@ -714,6 +714,20 @@ void clear_self_test_config(void)
}
void ipq_qca8075_dump_phy_regs(u32 phy_id)
{
u16 phy_data;
#define REG_LEN 9
u32 regs[REG_LEN] = { 0, 1, 2, 3, 4, 5, 6, 9, 10 };
int i;
for (i=0; i < REG_LEN; i++) {
phy_data = qca8075_phy_reg_read(0x0, phy_id, regs[i]);
printf("phy[%d] reg [%d] = 0x%x\n", phy_id, regs[i], phy_data);
}
#undef REG_LEN
}
int ipq_qca8075_phy_init(struct phy_ops **ops)
{
u16 phy_data;
@ -743,13 +757,6 @@ int ipq_qca8075_phy_init(struct phy_ops **ops)
QCA8075_PSGMII_FIFI_CTRL, phy_data);
}
/*
* Enable AZ transmitting ability
*/
qca8075_phy_mmd_write(0, PSGMII_ID, QCA8075_PHY_MMD1_NUM,
QCA8075_PSGMII_MODE_CTRL,
QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE);
/*
* Enable phy power saving function by default
*/
@ -760,12 +767,44 @@ int ipq_qca8075_phy_init(struct phy_ops **ops)
(qca8075_id == QCA8075_PHY_V1_1_5P) ||
(qca8075_id == QCA8075_PHY_V1_1_2P)) {
for (; phy_id < 5; phy_id++) {
/*enable phy power saving function by default */
qca8075_phy_set_8023az(0x0, phy_id, 0x1);
qca8075_phy_set_powersave(0x0, phy_id, 0x1);
qca8075_phy_set_hibernate(0x0, phy_id, 0x1);
/*
* change malibu control_dac[2:0] of MMD7 0x801A bit[9:7]
* from 111 to 101
*/
phy_data = qca8075_phy_mmd_read(0, phy_id,
QCA8075_PHY_MMD7_NUM, QCA8075_PHY_MMD7_DAC_CTRL);
phy_data &= ~QCA8075_DAC_CTRL_MASK;
phy_data |= QCA8075_DAC_CTRL_VALUE;
qca8075_phy_mmd_write(0, phy_id, QCA8075_PHY_MMD7_NUM,
QCA8075_PHY_MMD7_DAC_CTRL, phy_data);
/* add 10M and 100M link LED behavior for QFN board*/
phy_data = qca8075_phy_mmd_read(0, phy_id, QCA8075_PHY_MMD7_NUM,
QCA8075_PHY_MMD7_LED_1000_CTRL1);
phy_data &= ~QCA8075_LED_1000_CTRL1_100_10_MASK;
phy_data |= QCA8075_LED_1000_CTRL1_100_10_MASK;
qca8075_phy_mmd_write(0 , phy_id, QCA8075_PHY_MMD7_NUM,
QCA8075_PHY_MMD7_LED_1000_CTRL1, phy_data);
}
}
/*
* Enable AZ transmitting ability
*/
qca8075_phy_mmd_write(0, PSGMII_ID, QCA8075_PHY_MMD1_NUM,
QCA8075_PSGMII_MODE_CTRL,
QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE);
/* adjust psgmii serdes tx amp */
qca8075_phy_reg_write(0, 5, QCA8075_PSGMII_TX_DRIVER_1_CTRL,
QCA8075_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
/* to avoid psgmii module goes into hibernation, work with psgmii self test*/
phy_data = qca8075_phy_mmd_read(0, 4, QCA8075_PHY_MMD3_NUM, 0x805a);
phy_data &= (~(1 << 1));
qca8075_phy_mmd_write(0, 4, QCA8075_PHY_MMD3_NUM, 0x805a, phy_data);

13
drivers/net/ipq_common/ipq_qca8075.h
View file

@ -28,11 +28,11 @@
#define QCA8075_NEXT_PAGE_TRANSMIT 7
#define QCA8075_LINK_PARTNER_NEXT_PAGE 8
#define QCA8075_1000BASET_CONTROL 9
#define QCA8075_1000BASET_STATUS 10
#define QCA8075_1000BASET_STATUS 10
#define QCA8075_MMD_CTRL_REG 13
#define QCA8075_MMD_DATA_REG 14
#define QCA8075_EXTENDED_STATUS 15
#define QCA8075_PHY_SPEC_CONTROL 16
#define QCA8075_PHY_SPEC_CONTROL 16
#define QCA8075_PHY_SPEC_STATUS 17
#define QCA8075_PHY_INTR_MASK 18
#define QCA8075_PHY_INTR_STATUS 19
@ -473,6 +473,15 @@
#define QCA8075_INTR_WOL 0x0001
#define QCA8075_INTR_POE 0x0002
#define QCA8075_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define QCA8075_DAC_CTRL_MASK 0x380
#define QCA8075_PHY_MMD7_DAC_CTRL 0x801a
#define QCA8075_DAC_CTRL_VALUE 0x280
#define QCA8075_PHY_MMD7_NUM 7
#define QCA8075_PSGMII_TX_DRIVER_1_CTRL 0xb
#define QCA8075_PHY_MMD7_LED_1000_CTRL1 0x8076
#define QCA8075_LED_1000_CTRL1_100_10_MASK 0x30
#define RUN_CDT 0x8000
#define CABLE_LENGTH_UNIT 0x0400
#define QCA8075_MAX_TRIES 100

4
include/net.h
View file

@ -456,8 +456,8 @@ struct icmp_hdr {
* maximum packet size = 1518
* maximum packet size and multiple of 32 bytes = 1536
*/
#define PKTSIZE 1518
#define PKTSIZE_ALIGN 1536
#define PKTSIZE 2048
#define PKTSIZE_ALIGN 2048
/*#define PKTSIZE 608*/
/*