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ARM: qca: ipq8074: Added support for NOR+NAND

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Change includes
1. Device tree entry for SPI_NOR GPIO configuration
2. Register SPI_NOR as psudo NAND

Change-Id: I4d271dcd2970af370975e4a8d9a78199e1cfd2a2
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
This commit is contained in:
Gokul Sriram Palanisamy 2016-12-01 21:47:11 +05:30
parent de5e74d1b9
commit 5c0dd6970e
7 changed files with 76 additions and 7 deletions
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51
arch/arm/dts/ipq807x-soc.dtsi
View file

@ -31,6 +31,57 @@
timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
};
spi {
status = "ok";
compatible = "qcom,spi-qup-v2.7.0";
spi_gpio {
gpio1 {
gpio = <42>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
vm = <GPIO_VM_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES2>;
};
gpio2 {
gpio = <43>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
vm = <GPIO_VM_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES2>;
};
gpio3 {
gpio = <44>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
vm = <GPIO_VM_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES2>;
};
gpio4 {
gpio = <45>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
vm = <GPIO_VM_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES2>;
};
};
};
nand: nand-controller@79B0000 {
#address-cells = <1>;
#size-cells = <0>;

4
board/qca/common/fdt_fixup.c
View file

@ -232,8 +232,10 @@ int ft_board_setup(void *blob, bd_t *bd)
struct flash_node_info nodes[] = {
{ "qcom,msm-nand", MTD_DEV_TYPE_NAND, 0 },
{ "qcom,qcom_nand", MTD_DEV_TYPE_NAND, 0 },
{ "qcom,ebi2-nandc-bam-v1.5.0", MTD_DEV_TYPE_NAND, 0 },
{ "spinand,mt29f", MTD_DEV_TYPE_NAND, 1 },
{ "n25q128a11", MTD_DEV_TYPE_NAND, 2 },
{ "n25q128a11", MTD_DEV_TYPE_NAND,
CONFIG_IPQ_SPI_NOR_INFO_IDX },
{ NULL, 0, -1 }, /* Terminator */
};

10
board/qca/ipq807x/ipq807x.c
View file

@ -26,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
qca_mmc mmc_host;
extern int ipq_spi_init(u16);
const char *rsvd_node = "/reserved-memory";
const char *del_node[] = {"uboot",
"sbl"};
@ -108,7 +110,15 @@ int board_mmc_init(bd_t *bis)
void board_nand_init(void)
{
int gpio_node;
qpic_nand_init();
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
if (gpio_node >= 0) {
qca_gpio_init(gpio_node);
ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
}
}
void board_pci_init(int id)

2
drivers/mtd/Makefile
View file

@ -20,4 +20,4 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o
obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
obj-$(CONFIG_ST_SMI) += st_smi.o
obj-$(CONFIG_IPQ40XX_SPI) += ipq_spi_flash.o
obj-$(CONFIG_QCA_SPI) += ipq_spi_flash.o

5
drivers/spi/Makefile
View file

@ -32,7 +32,10 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_QCA_SPI) += qca_qup_spi.o
ifdef CONFIG_QCA_SPI
obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi.o
obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi.o
endif
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o

4
include/configs/ipq806x.h
View file

@ -251,10 +251,10 @@ typedef struct {
CONFIG_IPQ_MAX_SPI_DEVICE)
#define CONFIG_IPQ_NAND_NAND_INFO_IDX 0
#define CONFIG_IPQ_SPI_NAND_INFO_IDX 1
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_IPQ_NAND_NAND_INFO_IDX
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NAND_INFO_IDX
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
#define CONFIG_FDT_FIXUP_PARTITIONS

7
include/configs/ipq807x.h
View file

@ -100,6 +100,7 @@
#define CONFIG_QCA_SMEM_BASE 0x4AB00000
#define CONFIG_IPQ_FDT_HIGH 0x4A600000
#define CONFIG_IPQ_NO_MACS 1
#ifndef __ASSEMBLY__
@ -151,12 +152,14 @@ extern loff_t board_env_offset;
* Expose SPI driver as a pseudo NAND driver to make use
* of U-Boot's MTD framework.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE
#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \
CONFIG_IPQ_MAX_SPI_DEVICE
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 2
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX