ARM: net: ipq807x: Added ethernet support for hk-01 h/w

Added the ipq807x ethernet edma, ppe, gmac driver support
in the u-boot

Change-Id: I1d8ddd19f2c3d3765adda2253d3b71876142aa59
Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>

arch/arm/include/asm/arch-ipq807x/edma_regs.h

@@ -0,0 +1,398 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+*/
+
+#ifndef __EDMA_REGS__
+#define __EDMA_REGS__
+
+#define IPQ807X_EDMA_CFG_BASE			0x3ab00000
+/*
+ * IPQ807X EDMA register offsets
+ */
+#define IPQ807X_EDMA_REG_MAS_CTRL		0x0
+#define IPQ807X_EDMA_REG_PORT_CTRL		0x4
+#define IPQ807X_EDMA_REG_VLAN_CTRL		0x8
+#define IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_0	0xc
+#define IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_1	0x10
+#define IPQ807X_EDMA_REG_TXDESC2CMPL_MAP_2	0x14
+#define IPQ807X_EDMA_REG_RXDESC2FILL_MAP_0	0x18
+#define IPQ807X_EDMA_REG_RXDESC2FILL_MAP_1	0x1c
+#define IPQ807X_EDMA_REG_TXQ_CTRL		0x20
+#define IPQ807X_EDMA_REG_TXQ_CTRL_2		0x24
+#define IPQ807X_EDMA_REG_TXQ_FC_0		0x28
+#define IPQ807X_EDMA_REG_TXQ_FC_1		0x30
+#define IPQ807X_EDMA_REG_TXQ_FC_2		0x34
+#define IPQ807X_EDMA_REG_TXQ_FC_3		0x38
+#define IPQ807X_EDMA_REG_RXQ_CTRL		0x3c
+#define IPQ807X_EDMA_REG_RX_TX_FULL_QID		0x40
+#define IPQ807X_EDMA_REG_RXQ_FC_THRE		0x44
+#define IPQ807X_EDMA_REG_DMAR_CTRL		0x48
+#define IPQ807X_EDMA_REG_AXIR_CTRL		0x4c
+#define IPQ807X_EDMA_REG_AXIW_CTRL		0x50
+#define IPQ807X_EDMA_REG_MIN_MSS		0x54
+#define IPQ807X_EDMA_REG_LOOPBACK_CTRL		0x58
+#define IPQ807X_EDMA_REG_MISC_INT_STAT		0x5c
+#define IPQ807X_EDMA_REG_MISC_INT_MASK		0x60
+#define IPQ807X_EDMA_REG_DBG_CTRL		0x64
+#define IPQ807X_EDMA_REG_DBG_DATA		0x68
+#define IPQ807X_EDMA_REG_TXDESC_BA(n)		(0x1000 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXDESC_PROD_IDX(n)	(0x1004 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXDESC_CONS_IDX(n)	(0x1008 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXDESC_RING_SIZE(n)	(0x100c + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXDESC_CTRL(n)		(0x1010 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXCMPL_BA(n)		(0x19000 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXCMPL_PROD_IDX(n)	(0x19004 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXCMPL_CONS_IDX(n)	(0x19008 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXCMPL_RING_SIZE(n)	(0x1900c + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXCMPL_UGT_THRE(n)	(0x19010 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXCMPL_CTRL(n)		(0x19014 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TXCMPL_BPC(n)		(0x19018 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TX_INT_STAT(n)		(0x21000 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TX_INT_MASK(n)		(0x21004 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TX_MOD_TIMER(n)	(0x21008 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_TX_INT_CTRL(n)		(0x2100c + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_BA(n)		(0x29000 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_PROD_IDX(n)	(0x29004 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_CONS_IDX(n)	(0x29008 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_RING_SIZE(n)	(0x2900c + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_BUFFER1_SIZE(n)	(0x29010 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_FC_THRE(n)	(0x29014 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_UGT_THRE(n)	(0x29018 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_RING_EN(n)	(0x2901c + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_DISABLE(n)	(0x29020 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_DISABLE_DONE(n)	(0x29024 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_INT_STAT(n)	(0x31000 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXFILL_INT_MASK(n)	(0x31004 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_BA(n)		(0x39000 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_PROD_IDX(n)	(0x39004 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_CONS_IDX(n)	(0x39008 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_RING_SIZE(n)	(0x3900c + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_FC_THRE(n)	(0x39010 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_UGT_THRE(n)	(0x39014 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_CTRL(n)		(0x39018 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_BPC(n)		(0x3901c + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_INT_STAT(n)	(0x49000 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RXDESC_INT_MASK(n)	(0x49004 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RX_MOD_TIMER(n)	(0x49008 + (0x1000 * n))
+#define IPQ807X_EDMA_REG_RX_INT_CTRL(n)		(0x4900c + (0x1000 * n))
+#define IPQ807X_EDMA_QID2RID_TABLE_MEM(q)	(0x5a000 + (0x4 * q))
+#define IPQ807X_EDMA_REG_RXRING_PC(n)		(0x5A200 + (0x10 * n))
+#define IPQ807X_EDMA_REG_RXRING_BC_0(n)		(0x5A204 + (0x10 * n))
+#define IPQ807X_EDMA_REG_RXRING_BC_1(n)		(0x5A208 + (0x10 * n))
+#define IPQ807X_EDMA_REG_TXRING_PC(n)		(0x74000 + (0x10 * n))
+#define IPQ807X_EDMA_REG_TXRING_BC_0(n)		(0x74004 + (0x10 * n))
+#define IPQ807X_EDMA_REG_TXRING_BC_1(n)		(0x74008 + (0x10 * n))
+
+/*
+ * EDMA_REG_PORT_CTRL register
+ */
+#define IPQ807X_EDMA_PORT_CTRL_EN		0x3
+#define IPQ807X_EDMA_PORT_CTRL_PAD_EN		0x1
+
+/*
+ * EDMA_REG_TXQ_CTRL register
+ */
+#define IPQ807X_EDMA_TXDESC_PF_THRE_MASK		0xf
+#define IPQ807X_EDMA_TXDESC_PF_THRE_SHIFT		0
+#define IPQ807X_EDMA_TXCMPL_WB_THRE_MASK		0xf
+#define IPQ807X_EDMA_TXCMPL_WB_THRE_SHIFT		4
+#define IPQ807X_EDMA_TXDESC_PKT_SRAM_THRE_MASK		0xff
+#define IPQ807X_EDMA_TXDESC_PKT_SRAM_THRE_SHIFT		8
+#define IPQ807X_EDMA_TXCMPL_WB_TIMER_MASK		0xffff
+#define IPQ807X_EDMA_TXCMPL_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_CTRL register
+ */
+#define IPQ807X_EDMA_RXFILL_PF_THRE_MASK		0xf
+#define IPQ807X_EDMA_RXFILL_PF_THRE_SHIFT		0
+#define IPQ807X_EDMA_RXDESC_WB_THRE_MASK		0xf
+#define IPQ807X_EDMA_RXDESC_WB_THRE_SHIFT		4
+#define IPQ807X_EDMA_RXDESC_WB_TIMER_MASK		0xffff
+#define IPQ807X_EDMA_RXDESC_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RX_TX_FULL_QID register
+ */
+#define IPQ807X_EDMA_RX_DESC_FULL_QID_MASK		0xff
+#define IPQ807X_EDMA_RX_DESC_FULL_QID_SHIFT		0
+#define IPQ807X_EDMA_TX_CMPL_BUF_FULL_QID_MASK		0xff
+#define IPQ807X_EDMA_TX_CMPL_BUF_FULL_QID_SHIFT		8
+#define IPQ807X_EDMA_TX_SRAM_FULL_QID_MASK		0x1f
+#define IPQ807X_EDMA_TX_SRAM_FULL_QID_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_FC_THRE reister
+ */
+#define IPQ807X_EDMA_RXFILL_FIFO_XOFF_THRE_MASK		0x1f
+#define IPQ807X_EDMA_RXFILL_FIFO_XOFF_THRE_SHIFT	0
+#define IPQ807X_EDMA_DESC_FIFO_XOFF_THRE_MASK		0x3f
+#define IPQ807X_EDMA_DESC_FIFO_XOFF_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_DMAR_CTRL register
+ */
+#define IPQ807X_EDMA_DMAR_REQ_PRI_MASK			0x7
+#define IPQ807X_EDMA_DMAR_REQ_PRI_SHIFT			0
+#define IPQ807X_EDMA_DMAR_BURST_LEN_MASK		0x1
+#define IPQ807X_EDMA_DMAR_BURST_LEN_SHIFT		3
+#define IPQ807X_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK	0x1f
+#define IPQ807X_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT	4
+#define IPQ807X_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK	0x7
+#define IPQ807X_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT	9
+#define IPQ807X_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK	0x7
+#define IPQ807X_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT	12
+
+/*
+ * EDMA DISABLE
+ */
+#define IPQ807X_EDMA_DISABLE				0
+
+/*
+ * EDMA_REG_TXDESC_PROD_IDX register
+ */
+#define IPQ807X_EDMA_TXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CONS_IDX register
+ */
+#define IPQ807X_EDMA_TXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_RING_SIZE register
+ */
+#define IPQ807X_EDMA_TXDESC_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CTRL register
+ */
+#define IPQ807X_EDMA_TXDESC_ARB_GRP_ID_MASK		0x3
+#define IPQ807X_EDMA_TXDESC_ARB_GRP_ID_SHIFT		4
+#define IPQ807X_EDMA_TXDESC_FC_GRP_ID_MASK		0x7
+#define IPQ807X_EDMA_TXDESC_FC_GRP_ID_SHIFT		1
+#define IPQ807X_EDMA_TXDESC_TX_EN			0x1
+
+/*
+ * EDMA_REG_TXCMPL_PROD_IDX register
+ */
+#define IPQ807X_EDMA_TXCMPL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_CONS_IDX register
+ */
+#define IPQ807X_EDMA_TXCMPL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_RING_SIZE register
+ */
+#define IPQ807X_EDMA_TXCMPL_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_UGT_THRE register
+ */
+#define IPQ807X_EDMA_TXCMPL_LOW_THRE_MASK		0xffff
+#define IPQ807X_EDMA_TXCMPL_LOW_THRE_SHIFT		0
+#define IPQ807X_EDMA_TXCMPL_FC_THRE_MASK		0x3f
+#define IPQ807X_EDMA_TXCMPL_FC_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_TXCMPL_CTRL register
+ */
+#define IPQ807X_EDMA_TXCMPL_RET_MODE_BUFF_ADDR		0x0
+#define IPQ807X_EDMA_TXCMPL_RET_MODE_OPAQUE		0x1
+
+/*
+ * EDMA_REG_TX_MOD_TIMER register
+ */
+#define IPQ807X_EDMA_TX_MOD_TIMER_INIT_MASK		0xffff
+#define IPQ807X_EDMA_TX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA_REG_TX_INT_CTRL register
+ */
+#define IPQ807X_EDMA_TX_INT_MASK			0x3
+
+/*
+ * EDMA_REG_RXFILL_PROD_IDX register
+ */
+#define IPQ807X_EDMA_RXFILL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_CONS_IDX register
+ */
+#define IPQ807X_EDMA_RXFILL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_RING_SIZE register
+ */
+#define IPQ807X_EDMA_RXFILL_RING_SIZE_MASK		0xffff
+#define IPQ807X_EDMA_RXFILL_BUF_SIZE_MASK		0x3fff
+#define IPQ807X_EDMA_RXFILL_BUF_SIZE_SHIFT		16
+
+/*
+ * EDMA_REG_RXFILL_FC_THRE register
+ */
+#define IPQ807X_EDMA_RXFILL_FC_XON_THRE_MASK		0x7ff
+#define IPQ807X_EDMA_RXFILL_FC_XON_THRE_SHIFT		12
+#define IPQ807X_EDMA_RXFILL_FC_XOFF_THRE_MASK		0x7ff
+#define IPQ807X_EDMA_RXFILL_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_UGT_THRE register
+ */
+#define IPQ807X_EDMA_RXFILL_LOW_THRE_MASK		0xffff
+#define IPQ807X_EDMA_RXFILL_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_RING_EN register
+ */
+#define IPQ807X_EDMA_RXFILL_RING_EN			0x1
+
+/*
+ * EDMA_REG_RXFILL_INT_MASK register
+ */
+#define IPQ807X_EDMA_RXFILL_INT_MASK			0x1
+
+/*
+ * EDMA_REG_RXDESC_PROD_IDX register
+ */
+#define IPQ807X_EDMA_RXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_CONS_IDX register
+ */
+#define IPQ807X_EDMA_RXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_RING_SIZE register
+ */
+#define IPQ807X_EDMA_RXDESC_RING_SIZE_MASK		0xffff
+#define IPQ807X_EDMA_RXDESC_PL_OFFSET_MASK		0x1ff
+#define IPQ807X_EDMA_RXDESC_PL_OFFSET_SHIFT		16
+
+/*
+ * EDMA_REG_RXDESC_FC_THRE register
+ */
+#define IPQ807X_EDMA_RXDESC_FC_XON_THRE_MASK		0x7ff
+#define IPQ807X_EDMA_RXDESC_FC_XON_THRE_SHIFT		12
+#define IPQ807X_EDMA_RXDESC_FC_XOFF_THRE_MASK		0x7ff
+#define IPQ807X_EDMA_RXDESC_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_UGT_THRE register
+ */
+#define IPQ807X_EDMA_RXDESC_LOW_THRE_MASK		0xffff
+#define IPQ807X_EDMA_RXDESC_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_CTRL register
+ */
+#define IPQ807X_EDMA_RXDESC_STAG_REMOVE_EN		0x8
+#define IPQ807X_EDMA_RXDESC_CTAG_REMOVE_EN		0x4
+#define IPQ807X_EDMA_RXDESC_QDISC_EN			0x2
+#define IPQ807X_EDMA_RXDESC_RX_EN			0x1
+
+/*
+ * EDMA_REG_TX_INT_MASK register
+ */
+#define IPQ807X_EDMA_TX_INT_MASK_PKT_INT		0x1
+#define IPQ807X_EDMA_TX_INT_MASK_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_STAT register
+ */
+#define IPQ807X_EDMA_RXDESC_INT_STAT_PKT_INT		0x1
+#define IPQ807X_EDMA_RXDESC_INT_STAT_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_MASK register
+ */
+#define IPQ807X_EDMA_RXDESC_INT_MASK_PKT_INT		0x1
+#define IPQ807X_EDMA_RXDESC_INT_MASK_TIMER_INT_DIS	0x2
+
+#define IPQ807X_EDMA_MASK_INT_DISABLE			0x0
+#define IPQ807X_EDMA_MASK_INT_CLEAR			0x0
+
+/*
+ * EDMA_REG_RX_MOD_TIMER register
+ */
+#define IPQ807X_EDMA_RX_MOD_TIMER_INIT_MASK		0xffff
+#define IPQ807X_EDMA_RX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA QID2RID register sizes
+ */
+#define IPQ807X_EDMA_QID2RID_DEPTH			0x40
+#define IPQ807X_EDMA_QID2RID_QUEUES_PER_ENTRY		8
+
+/*
+ * TXDESC shift values
+ */
+#define IPQ807X_EDMA_TXDESC_MORE_SHIFT			31
+#define IPQ807X_EDMA_TXDESC_TSO_EN_SHIFT		30
+#define IPQ807X_EDMA_TXDESC_PREHEADER_SHIFT		29
+#define IPQ807X_EDMA_TXDESC_POOL_ID_SHIFT		24
+#define IPQ807X_EDMA_TXDESC_POOL_ID_MASK		0x1f
+#define IPQ807X_EDMA_TXDESC_DATA_OFFSET_SHIFT		16
+#define IPQ807X_EDMA_TXDESC_DATA_OFFSET_MASK		0xff
+#define IPQ807X_EDMA_TXDESC_DATA_LENGTH_SHIFT		0
+#define IPQ807X_EDMA_TXDESC_DATA_LENGTH_MASK		0xffff
+
+#define IPQ807X_EDMA_PREHDR_DSTINFO_PORTID_IND		0x20
+#define IPQ807X_EDMA_PREHDR_PORTNUM_BITS		0x0fff
+#define IPQ807X_EDMA_RING_DMA_MASK			0xffffffff
+/*
+ * RXDESC shift values
+ */
+#define IPQ807X_EDMA_RXDESC_RX_RXFILL_CNT_MASK		0x000f
+#define IPQ807X_EDMA_RXDESC_RX_RXFILL_CNT_SHIFT		16
+
+#define IPQ807X_EDMA_RXDESC_PKT_SIZE_MASK		0x3fff
+#define IPQ807X_EDMA_RXDESC_PKT_SIZE_SHIFT		0
+
+#define IPQ807X_EDMA_RXDESC_RXD_VALID_MASK		0x1
+#define IPQ807X_EDMA_RXDESC_RXD_VALID_SHIFT		31
+
+#define IPQ807X_EDMA_RXDESC_PACKET_LEN_MASK		0x3fff
+#define IPQ807X_EDMA_RXDESC_RING_INT_STATUS_MASK	0x3
+
+#define IPQ807X_EDMA_RING_DISABLE			0
+#define IPQ807X_EDMA_TXCMPL_RING_INT_STATUS_MASK	0x3
+#define IPQ807X_EDMA_TXCMPL_RETMODE_OPAQUE		0x0
+#define IPQ807X_EDMA_RXFILL_RING_INT_STATUS_MASK	0x1
+
+/*
+ * TODO tune the timer and threshold values
+ */
+#define IPQ807X_EDMA_RXFILL_FIFO_XOFF_THRE		0x3
+#define IPQ807X_EDMA_RXFILL_PF_THRE			0x3
+#define IPQ807X_EDMA_RXDESC_WB_THRE			0x0
+#define IPQ807X_EDMA_RXDESC_WB_TIMER			0x2
+
+#define IPQ807X_EDMA_RXDESC_XON_THRE			50
+#define IPQ807X_EDMA_RXDESC_XOFF_THRE			30
+#define IPQ807X_EDMA_RXDESC_LOW_THRE			0
+#define IPQ807X_EDMA_RX_MOD_TIMER_INIT			1000
+
+#define IPQ807X_EDMA_TXDESC_PF_THRE			0x3
+#define IPQ807X_EDMA_TXCMPL_WB_THRE			0X0
+#define IPQ807X_EDMA_TXDESC_PKT_SRAM_THRE		0x20
+#define IPQ807X_EDMA_TXCMPL_WB_TIMER			0x2
+
+#define IPQ807X_EDMA_TX_MOD_TIMER			150
+
+#endif /*  __EDMA_REGS__ */

board/qca/arm/ipq807x/ipq807x.c

@@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 qca_mmc mmc_host;
 
 extern int ipq_spi_init(u16);
+extern int ipq807x_edma_init(void *cfg);
 
 const char *rsvd_node = "/reserved-memory";
 const char *del_node[] = {"uboot",
@@ -94,6 +95,18 @@ void emmc_clock_config(int mode)
 	udelay(10);
 }
 
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	ret = ipq807x_edma_init(NULL);
+
+	if (ret != 0)
+		printf("%s: ipq807x_edma_init failed : %d\n", __func__, ret);
+
+	return ret;
+}
+
 int board_mmc_init(bd_t *bis)
 {
 	int ret;

drivers/net/Makefile

@@ -82,3 +82,5 @@ obj-$(CONFIG_IPQ40XX_MDIO) += ipq40xx/ipq40xx_mdio.o
 obj-$(CONFIG_IPQ_SNPS_GMAC) += ipq806x/ipq_gmac_eth.o
 obj-$(CONFIG_IPQ_SWITCH_ATHRS17) += ipq806x/athrs17_phy.o
 obj-$(CONFIG_IPQ_SWITCH_QCA8511) += ipq806x/qca8511.o
+obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_edma.o
+obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_ppe.o

drivers/net/ipq807x/ipq807x_edma.h

@@ -0,0 +1,301 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+*/
+#ifndef __IPQ807X_EDMA__
+#define __IPQ807X_EDMA__
+
+#define IPQ807X_NSS_DP_START_PHY_PORT   1
+#define IPQ807X_NSS_DP_MAX_PHY_PORTS    6
+
+#define IPQ807X_EDMA_BUF_SIZE		2000
+#define IPQ807X_EDMA_DEVICE_NODE_NAME	"edma"
+#define IPQ807X_EDMA_RX_BUFF_SIZE	(IPQ807X_EDMA_BUF_SIZE + IPQ807X_EDMA_RX_PREHDR_SIZE)
+#define IPQ807X_EDMA_RX_PREHDR_SIZE	(sizeof(struct ipq807x_edma_rx_preheader))
+#define IPQ807X_EDMA_TX_PREHDR_SIZE	(sizeof(struct ipq807x_edma_tx_preheader))
+
+#define IPQ807X_EDMA_TXDESC_RING_SIZE	8
+#define IPQ807X_EDMA_TXCMPL_RING_SIZE	8
+#define IPQ807X_EDMA_RXDESC_RING_SIZE	16
+#define IPQ807X_EDMA_RXFILL_RING_SIZE	16
+
+#define IPQ807X_EDMA_START_GMACS	IPQ807X_NSS_DP_START_PHY_PORT
+#define IPQ807X_EDMA_MAX_GMACS		IPQ807X_NSS_DP_MAX_PHY_PORTS
+#define IPQ807X_EDMA_TX_BUF_SIZE	(1540 + IPQ807X_EDMA_TX_PREHDR_SIZE)
+
+#define IPQ807X_EDMA_MAX_TXCMPL_RINGS	8	/* Max TxCmpl rings */
+#define IPQ807X_EDMA_MAX_RXDESC_RINGS	16	/* Max RxDesc rings */
+#define IPQ807X_EDMA_MAX_RXFILL_RINGS	8	/* Max RxFill rings */
+#define IPQ807X_EDMA_MAX_TXDESC_RINGS	24	/* Max TxDesc rings */
+
+#define IPQ807X_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
+#define IPQ807X_EDMA_RXFILL_DESC(R, i) 	IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_rxfill_desc)
+#define IPQ807X_EDMA_RXDESC_DESC(R, i) 	IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_rxdesc_desc)
+#define IPQ807X_EDMA_TXDESC_DESC(R, i) 	IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_txdesc_desc)
+#define IPQ807X_EDMA_TXCMPL_DESC(R, i) 	IPQ807X_EDMA_GET_DESC(R, i, struct ipq807x_edma_txcmpl_desc)
+#define IPQ807X_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph)	(((rxph)->src_info >> 8) & 0xf0)
+
+#define IPQ807X_EDMA_DEV		1
+#define IPQ807X_EDMA_TX_QUEUE		1
+#define IPQ807X_EDMA_RX_QUEUE		1
+
+//#define IPQ807X_EDMA_TX_DESC_RING_START	23
+#define IPQ807X_EDMA_TX_DESC_RING_START	0
+#define IPQ807X_EDMA_TX_DESC_RING_NOS	1
+#define IPQ807X_EDMA_TX_DESC_RING_SIZE	\
+(IPQ807X_EDMA_TX_DESC_RING_START + IPQ807X_EDMA_TX_DESC_RING_NOS)
+
+#define IPQ807X_EDMA_TX_CMPL_RING_START	7
+#define IPQ807X_EDMA_TX_CMPL_RING_NOS	1
+#define IPQ807X_EDMA_TX_CMPL_RING_SIZE	\
+(IPQ807X_EDMA_TX_CMPL_RING_START + IPQ807X_EDMA_TX_CMPL_RING_NOS)
+
+#define IPQ807X_EDMA_RX_DESC_RING_START	15
+#define IPQ807X_EDMA_RX_DESC_RING_NOS	1
+#define IPQ807X_EDMA_RX_DESC_RING_SIZE	\
+(IPQ807X_EDMA_RX_DESC_RING_START + IPQ807X_EDMA_RX_DESC_RING_NOS)
+
+#define IPQ807X_EDMA_RX_FILL_RING_START	7
+#define IPQ807X_EDMA_RX_FILL_RING_NOS	1
+#define IPQ807X_EDMA_RX_FILL_RING_SIZE	\
+(IPQ807X_EDMA_RX_FILL_RING_START + IPQ807X_EDMA_RX_FILL_RING_NOS)
+
+#define IPQ807X_EDMA_TX_IMR_NORMAL_MASK	1
+#define IPQ807X_EDMA_RX_IMR_NORMAL_MASK	1
+#define IPQ807X_EDMA_INTR_CLEAR_TYPE	0
+#define IPQ807X_EDMA_INTR_SW_IDX_W_TYPE	0
+#define IPQ807X_EDMA_RSS_TYPE_NONE	0x1
+
+#define NETDEV_TX_BUSY	1
+
+/*
+ * Tx descriptor
+ */
+struct ipq807x_edma_txdesc_desc {
+	uint32_t buffer_addr;
+		/* buffer address */
+	uint32_t word1;
+		/* more bit, TSO, preheader, pool, offset and length */
+};
+
+/*
+ * TxCmpl descriptor
+ */
+struct ipq807x_edma_txcmpl_desc {
+	uint32_t buffer_addr;	/* buffer address/opaque */
+	uint32_t status;	/* status */
+};
+
+/*
+ * Rx descriptor
+ */
+struct ipq807x_edma_rxdesc_desc {
+	uint32_t buffer_addr;	/* buffer address */
+	uint32_t status;	/* status */
+};
+
+/*
+ * RxFill descriptor
+ */
+struct ipq807x_edma_rxfill_desc {
+	uint32_t buffer_addr;	/* Buffer address */
+	uint32_t word1;		/* opaque_ind and buffer size */
+};
+
+/*
+ * Tx descriptor ring
+ */
+struct ipq807x_edma_txdesc_ring {
+	uint32_t id;			/* TXDESC ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors */
+};
+
+/*
+ * TxCmpl ring
+ */
+struct ipq807x_edma_txcmpl_ring {
+	uint32_t id;			/* TXCMPL ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * RxFill ring
+ */
+struct ipq807x_edma_rxfill_ring {
+	uint32_t id;			/* RXFILL ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * RxDesc ring
+ */
+struct ipq807x_edma_rxdesc_ring {
+	uint32_t id;			/* RXDESC ring number */
+	struct ipq807x_edma_rxfill_ring *rxfill;	/* RXFILL ring used */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * EDMA Tx Preheader
+ */
+struct ipq807x_edma_tx_preheader {
+	uint32_t opaque;   /* Opaque, contains skb pointer */
+	uint16_t src_info; /* Src information */
+	uint16_t dst_info; /* Dest information */
+	uint32_t tx_pre2;  /* SVLAN & CVLAN flag, drop prec, hash value */
+	uint32_t tx_pre3;  /* STAG, CTAG */
+	uint32_t tx_pre4;  /* CPU code, L3 & L4 offset, service code */
+	uint32_t tx_pre5;  /* IP addr index, ACL index */
+	uint32_t tx_pre6;  /* IP payload checksum, copy2cpu, timestamp, dscp */
+	uint32_t tx_pre7;  /* Timestamp, QoS TAG */
+};
+
+/*
+ * EDMA Rx Preheader
+ */
+struct ipq807x_edma_rx_preheader {
+	uint32_t opaque; /* Opaque, contains skb pointer*/
+	uint16_t src_info; /* Src information */
+	uint16_t dst_info; /* Dest information */
+	uint32_t rx_pre2; /* SVLAN & CVLAN flag, drop prec, hash value */
+	uint32_t rx_pre3; /* STAG, CTAG */
+	uint32_t rx_pre4; /* CPU code, L3 & L4 offset, service code */
+	uint32_t rx_pre5; /* IP addr index, ACL index */
+	uint32_t rx_pre6; /* IP payload checksum, copy2cpu, timestamp, dscp */
+	uint32_t rx_pre7; /* Timestamp, QoS TAG */
+};
+
+enum ipq807x_edma_tx {
+	EDMA_TX_OK = 0,		/* Tx success */
+	EDMA_TX_DESC = 1,	/* Not enough descriptors */
+	EDMA_TX_FAIL = 2,	/* Tx failure */
+};
+
+
+/* per core queue related information */
+struct queue_per_cpu_info {
+	u32 tx_mask; /* tx interrupt mask */
+	u32 rx_mask; /* rx interrupt mask */
+	u32 tx_status; /* tx interrupt status */
+	u32 rx_status; /* rx interrupt status */
+	u32 tx_start; /* tx queue start */
+	u32 rx_start; /* rx queue start */
+	struct ipq807x_edma_common_info *c_info; /* edma common info */
+};
+
+/* edma hw specific data */
+struct ipq807x_edma_hw {
+	unsigned long  __iomem *hw_addr; /* inner register address */
+	u8 intr_clear_type; /* interrupt clear */
+	u8 intr_sw_idx_w; /* To do chk type interrupt software index */
+	u16 rx_buff_size; /* To do chk type Rx buffer size */
+	u8 rss_type; /* rss protocol type */
+	uint16_t rx_payload_offset; /* start of the payload offset */
+	uint32_t flags; /* internal flags */
+	int active; /* status */
+	struct ipq807x_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */
+	struct ipq807x_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */
+	struct ipq807x_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */
+	struct ipq807x_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */
+	uint32_t txdesc_rings; /* Number of TxDesc rings */
+	uint32_t txdesc_ring_start; /* Id of first TXDESC ring */
+	uint32_t txdesc_ring_end; /* Id of the last TXDESC ring */
+	uint32_t txcmpl_rings; /* Number of TxCmpl rings */
+	uint32_t txcmpl_ring_start; /* Id of first TXCMPL ring */
+	uint32_t txcmpl_ring_end; /* Id of last TXCMPL ring */
+	uint32_t rxfill_rings; /* Number of RxFill rings */
+	uint32_t rxfill_ring_start; /* Id of first RxFill ring */
+	uint32_t rxfill_ring_end; /* Id of last RxFill ring */
+	uint32_t rxdesc_rings; /* Number of RxDesc rings */
+	uint32_t rxdesc_ring_start; /* Id of first RxDesc ring */
+	uint32_t rxdesc_ring_end; /* Id of last RxDesc ring */
+	uint32_t tx_intr_mask; /* tx interrupt mask */
+	uint32_t rx_intr_mask; /* rx interrupt mask */
+	uint32_t rxfill_intr_mask; /* Rx fill ring interrupt mask */
+	uint32_t rxdesc_intr_mask; /* Rx Desc ring interrupt mask */
+	uint32_t txcmpl_intr_mask; /* Tx Cmpl ring interrupt mask */
+	uint32_t misc_intr_mask; /* misc interrupt interrupt mask */
+};
+
+struct ipq807x_edma_common_info {
+	struct ipq807x_edma_hw hw;
+};
+
+struct ipq807x_eth_dev {
+	u8 *phy_address;
+	uint no_of_phys;
+	uint interface;
+	uint speed;
+	uint duplex;
+	uint sw_configured;
+	uint mac_unit;
+	uint mac_ps;
+	int link_printed;
+	u32 padding;
+	struct eth_device *dev;
+	struct ipq807x_edma_common_info *c_info;
+	struct phy_ops *ops;
+	const char phy_name[MDIO_NAME_LEN];
+} __attribute__ ((aligned(8)));
+
+static inline void* ipq807x_alloc_mem(u32 size)
+{
+	void *p = malloc(size);
+	if (p != NULL)
+		memset(p, 0, size);
+	return p;
+}
+
+static inline void ipq807x_free_mem(void *ptr)
+{
+	if (ptr)
+		free(ptr);
+}
+
+//extern struct ipq807x_edma_hw ipq807x_edma_hw;
+
+uint32_t ipq807x_edma_reg_read(uint32_t reg_off);
+void ipq807x_edma_reg_write(uint32_t reg_off, uint32_t val);
+
+
+extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs);
+
+typedef struct {
+	uint count;
+	u8 addr[7];
+} ipq807x_edma_phy_addr_t;
+
+/* ipq807x edma Paramaters */
+typedef struct {
+	uint base;
+	int unit;
+	uint mac_conn_to_phy;
+	phy_interface_t phy;
+	ipq807x_edma_phy_addr_t phy_addr;
+	const char phy_name[MDIO_NAME_LEN];
+} ipq807x_edma_board_cfg_t;
+
+extern void ipq807x_ppe_provision_init(void);
+
+#endif /* ___IPQ807X_EDMA__ */

drivers/net/ipq807x/ipq807x_ppe.c

@@ -0,0 +1,969 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <common.h>
+#include "ipq807x_ppe.h"
+
+#define pr_info(fmt, args...) printf(fmt, ##args);
+
+/*
+ * ipq807x_ppe_gpio_reg_write()
+ */
+static inline void ipq807x_ppe_gpio_reg_write(u32 reg, u32 val)
+{
+	writel(val, IPQ807X_PPE_FPGA_GPIO_BASE_ADDR + reg);
+}
+
+/*
+ * ipq807x_ppe_reg_read()
+ */
+static inline void ipq807x_ppe_reg_read(u32 reg, u32 *val)
+{
+	*val = readl((void *)(IPQ807X_PPE_BASE_ADDR + reg));
+}
+
+/*
+ * ipq807x_ppe_reg_write()
+ */
+static inline void ipq807x_ppe_reg_write(u32 reg, u32 val)
+{
+	writel(val, (void *)(IPQ807X_PPE_BASE_ADDR + reg));
+}
+
+/*
+ * ipq807x_ppe_vp_port_tbl_set()
+ */
+static void ipq807x_ppe_vp_port_tbl_set(int port, int vsi)
+{
+	u32 addr = IPQ807X_PPE_L3_VP_PORT_TBL_ADDR +
+		 (port * IPQ807X_PPE_L3_VP_PORT_TBL_INC);
+	ipq807x_ppe_reg_write(addr, 0x0);
+	ipq807x_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10);
+	ipq807x_ppe_reg_write(addr + 0x8, 0x0);
+}
+
+/*
+ * ipq807x_ppe_ucast_queue_map_tbl_queue_id_set()
+ */
+static void ipq807x_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port)
+{
+	uint32_t val;
+
+	ipq807x_ppe_reg_read(IPQ807X_PPE_QM_UQM_TBL +
+		 (port * IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_INC), &val);
+
+	val |= queue << 4;
+
+	ipq807x_ppe_reg_write(IPQ807X_PPE_QM_UQM_TBL +
+		 (port * IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_INC), val);
+}
+
+/*
+ * ipq807x_vsi_setup()
+ */
+static void ipq807x_vsi_setup(int vsi, uint8_t group_mask)
+{
+	uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8
+							    | group_mask);
+
+	/* Set mask */
+	ipq807x_ppe_reg_write(0x061800 + (vsi * 0x10), val);
+
+	/*  new addr lrn en | station move lrn en */
+	ipq807x_ppe_reg_write(0x061804 + (vsi * 0x10), 0x9);
+}
+
+/*
+ * ipq807x_gmac_enable()
+ */
+
+static void ipq807x_gmac_enable(void)
+{
+	writel(0x0, 0x1008004);
+}
+
+/*
+ * ipq807x_gmac_port_enable()
+ */
+static void ipq807x_gmac_port_enable(int port)
+{
+	ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_ENABLE + (0x200 * port), 0x13);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_SPEED + (0x200 * port), 0x2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
+}
+
+/*
+ * ipq807x_ppe_flow_port_map_tbl_port_num_set()
+ */
+static void ipq807x_ppe_flow_port_map_tbl_port_num_set(int queue, int port)
+{
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL +
+			queue * IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_INC, port);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL +
+			port * IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_INC, port);
+}
+
+/*
+ * ipq807x_ppe_flow_map_tbl_set()
+ */
+static void ipq807x_ppe_flow_map_tbl_set(int queue, int port)
+{
+	uint32_t val = port | 0x401000; /* c_drr_wt = 1, e_drr_wt = 1 */
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L0_FLOW_MAP_TBL + queue * IPQ807X_PPE_L0_FLOW_MAP_TBL_INC,
+									val);
+
+	val = port | 0x100400; /* c_drr_wt = 1, e_drr_wt = 1 */
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L1_FLOW_MAP_TBL + port * IPQ807X_PPE_L1_FLOW_MAP_TBL_INC,
+									val);
+}
+
+/*
+ * ipq807x_ppe_tdm_configuration
+ */
+static void ipq807x_ppe_tdm_configuration(void)
+{
+	int i = 0;
+
+	/*
+	 * TDM is configured with instructions for each tick
+	 * Port/action are configured as given below
+	 *
+	 * 0x5:0x5	TDM_CFG_VALID		0:idle tick
+	 * 0x4:0x4	TDM_CFG_DIR		0:ingress wr
+	 *					1:egress rd
+	 * 0x3:0x0	TDM_CFG_PORT_NUM	0:DMA
+	 *					1~4:Ethernet 1G
+	 *					5~6:Ethernet 5G
+	 *					7~8:Security0/1
+	 */
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_QCOM1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_QCOM3);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_QCOM2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_QCOM4);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID
+			| IPQ807X_PPE_TDM_CFG_DIR_EGRESS
+			| IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_QCOM1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_QCOM3);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_QCOM2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_QCOM4);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_INGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
+			IPQ807X_PPE_TDM_CFG_VALID |
+			IPQ807X_PPE_TDM_CFG_DIR_EGRESS |
+			IPQ807X_PPE_PORT_CRYPTO1);
+
+	/* Set TDM Depth to 100 entries */
+	ipq807x_ppe_reg_write(IPQ807X_PPE_TDM_CFG_DEPTH_OFFSET, IPQ807X_PPE_TDM_CFG_DEPTH_VAL);
+}
+
+/*
+ * ipq807x_ppe_sched_configuration
+ */
+static void ipq807x_ppe_sched_configuration(void)
+{
+	int i = 0;
+
+	/*
+	 * PSCH_TDM_CFG_TBL_DES_PORT : determine which egress port traffic
+	 *			will be selected and transmitted out
+	 * PSCH_TDM_CFG_TBL_ENS_PORT : determine which port’s queue need
+	 *			to be linked to scheduler at the current tick
+	 * PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP : determine port bitmap
+	 *			for source of queue
+	 *
+	 * 0xf:0x8	PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP	1110_1110
+	 *							(Port:765-432)
+	 *
+	 * 0x7:0x4	PSCH_TDM_CFG_TBL_ENS_PORT		0:DMA
+	 *							1~4:Ethernet 1G
+	 *							5~6:Ethernet 5G
+	 *							7~8:Security0/1
+	 *
+	 * 0x3:0x0	PSCH_TDM_CFG_TBL_DES_PORT		0:DMA
+	 *							1~4:Ethernet 1G
+	 *							5~6:Ethernet 5G
+	 *							7~8:Security0/1
+	 *
+	 * For eg, 0xee60 =((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+	 *		IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+	 *		IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+	 *		IPQ807X_PPE_PORT_XGMAC2 | IPQ807X_PPE_PORT_EDMA);
+	 */
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM3_BITPOS | IPQ807X_PPE_PORT_QCOM2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM4 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_QCOM4_BITPOS |
+			IPQ807X_PPE_PORT_QCOM3_BITPOS | IPQ807X_PPE_PORT_QCOM2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_QCOM1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM1 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA  << 4) | IPQ807X_PPE_PORT_QCOM2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM2 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_QCOM3);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM3 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_QCOM4);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM4 << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM2_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_QCOM1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM1 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_QCOM2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM2 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_XGMAC1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_CRYPTO1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_XGMAC2_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_CRYPTO1 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_QCOM3);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC2 << 4) | IPQ807X_PPE_PORT_EDMA);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC2_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_QCOM3 << 4) | IPQ807X_PPE_PORT_XGMAC1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_EDMA_BITPOS |
+			IPQ807X_PPE_PORT_QCOM4_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_EDMA << 4) | IPQ807X_PPE_PORT_XGMAC2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
+			((IPQ807X_PPE_PORT_CRYPTO1_BITPOS | IPQ807X_PPE_PORT_XGMAC1_BITPOS |
+			IPQ807X_PPE_PORT_EDMA_BITPOS | IPQ807X_PPE_PORT_QCOM3_BITPOS |
+			IPQ807X_PPE_PORT_QCOM2_BITPOS | IPQ807X_PPE_PORT_QCOM1_BITPOS) << 8) |
+			(IPQ807X_PPE_PORT_XGMAC1 << 4) | IPQ807X_PPE_PORT_QCOM4);
+
+	/* Set Sched Depth to 50 entries */
+	ipq807x_ppe_reg_write(IPQ807X_PPE_TDM_SCHED_DEPTH_OFFSET, IPQ807X_PPE_TDM_SCHED_DEPTH_VAL);
+}
+
+/*
+ * ipq807x_ppe_c_sp_cfg_tbl_drr_id_set
+ */
+static void ipq807x_ppe_c_sp_cfg_tbl_drr_id_set(int id)
+{
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L0_C_SP_CFG_TBL + (id * 0x80), id * 2);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L1_C_SP_CFG_TBL + (id * 0x80), id * 2);
+}
+
+/*
+ * ipq807x_ppe_e_sp_cfg_tbl_drr_id_set
+ */
+static void ipq807x_ppe_e_sp_cfg_tbl_drr_id_set(int id)
+{
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L0_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
+	ipq807x_ppe_reg_write(IPQ807X_PPE_L1_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
+}
+
+/*
+ * ipq807x_ppe_provision_init()
+ */
+void ipq807x_ppe_provision_init(void)
+{
+	int i;
+	uint32_t queue;
+
+	/* Port4 Port5, Port6 port mux configuration, all GMAC */
+	writel(0x3d, 0x3a000010);
+
+	/* tdm/sched configuration */
+	ipq807x_ppe_tdm_configuration();
+	ipq807x_ppe_sched_configuration();
+
+	ipq807x_gmac_enable();
+
+	/* disable clock gating */
+	ipq807x_ppe_reg_write(0x000008, 0x0);
+
+	/* flow ctrl disable */
+	ipq807x_ppe_reg_write(0x200368, 0xc88);
+
+#ifdef CONFIG_IPQ807X_BRIDGED_MODE
+	/* Add CPU port 0 to VSI 2 */
+	ipq807x_ppe_vp_port_tbl_set(0, 2);
+
+	/* Add port 1 - 4 to VSI 2 */
+	ipq807x_ppe_vp_port_tbl_set(1, 2);
+	ipq807x_ppe_vp_port_tbl_set(2, 2);
+	ipq807x_ppe_vp_port_tbl_set(3, 2);
+	ipq807x_ppe_vp_port_tbl_set(4, 2);
+
+#else
+	ipq807x_ppe_vp_port_tbl_set(1, 2);
+	ipq807x_ppe_vp_port_tbl_set(2, 3);
+	ipq807x_ppe_vp_port_tbl_set(3, 4);
+	ipq807x_ppe_vp_port_tbl_set(4, 5);
+#endif
+
+	/* Unicast priority map */
+	ipq807x_ppe_reg_write(IPQ807X_PPE_QM_UPM_TBL, 0);
+
+	/* Port0 - 7 unicast queue settings */
+	for (i = 0; i < 8; i++) {
+		if (i == 0)
+			queue = 0;
+		else
+			queue = ((i * 0x10) + 0x70);
+
+		ipq807x_ppe_ucast_queue_map_tbl_queue_id_set(queue, i);
+		ipq807x_ppe_flow_port_map_tbl_port_num_set(queue, i);
+		ipq807x_ppe_flow_map_tbl_set(queue, i);
+		ipq807x_ppe_c_sp_cfg_tbl_drr_id_set(i);
+		ipq807x_ppe_e_sp_cfg_tbl_drr_id_set(i);
+	}
+
+	/* Port0 multicast queue */
+	ipq807x_ppe_reg_write(0x409000, 0x00000000);
+	ipq807x_ppe_reg_write(0x403000, 0x00401000);
+
+	/* Port1 - 7 multicast queue */
+	for (i = 1; i < 8; i++) {
+		ipq807x_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i);
+		ipq807x_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i);
+	}
+
+	/*
+	 * Port0 - Port7 learn enable and isolation port bitmap and TX_EN
+	 * Here please pay attention on bit16 (TX_EN) is not set on port7
+	 */
+	for (i = 0; i < 7; i++)
+		ipq807x_ppe_reg_write(IPQ807X_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
+			      IPQ807X_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
+			      IPQ807X_PPE_PORT_BRIDGE_CTRL_TXMAC_EN |
+			      IPQ807X_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
+			      IPQ807X_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
+			      IPQ807X_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
+
+	ipq807x_ppe_reg_write(IPQ807X_PPE_PORT_BRIDGE_CTRL_OFFSET + (7 * 4),
+		      IPQ807X_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
+		      IPQ807X_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
+		      IPQ807X_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
+		      IPQ807X_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
+
+	/* Global learning */
+	ipq807x_ppe_reg_write(0x060038, 0xc0);
+
+#ifdef CONFIG_IPQ807X_BRIDGED_MODE
+	ipq807x_vsi_setup(2, 0x1f);
+#else
+	ipq807x_vsi_setup(2, 0x03);
+	ipq807x_vsi_setup(3, 0x05);
+	ipq807x_vsi_setup(4, 0x09);
+	ipq807x_vsi_setup(5, 0x11);
+#endif
+
+	/* Port 0-7 STP */
+	for (i = 0; i < 8; i++)
+		ipq807x_ppe_reg_write(IPQ807X_PPE_STP_BASE + (0x4 * i), 0x3);
+
+	/* Port 0-5 enable */
+	for (i = 0; i < 6; i++)
+		ipq807x_gmac_port_enable(i);
+}

drivers/net/ipq807x/ipq807x_ppe.h

@@ -0,0 +1,124 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <common.h>
+#include <net.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <phy.h>
+#include <net.h>
+#include <miiphy.h>
+
+#define IPQ807X_PPE_BASE_ADDR			0x3a000000
+#define IPQ807X_PPE_REG_SIZE			0x1000000
+
+#define IPQ807X_PPE_IPE_L3_BASE_ADDR		0x200000
+#define IPQ807X_PPE_L3_VP_PORT_TBL_ADDR		(IPQ807X_PPE_IPE_L3_BASE_ADDR + 0x1000)
+#define IPQ807X_PPE_L3_VP_PORT_TBL_INC		0x10
+
+#define IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR	0x800000
+#define IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_ADDR	0x10000
+#define IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_INC	0x10
+#define IPQ807X_PPE_QM_UQM_TBL			(IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_ADDR)
+#define IPQ807X_PPE_UCAST_PRIORITY_MAP_TBL_ADDR	0x42000
+#define IPQ807X_PPE_QM_UPM_TBL			(IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_UCAST_PRIORITY_MAP_TBL_ADDR)
+
+#define IPQ807X_PPE_STP_BASE			0x060100
+#define IPQ807X_PPE_MAC_ENABLE			0x001000
+#define IPQ807X_PPE_MAC_SPEED			0x001004
+#define IPQ807X_PPE_MAC_MIB_CTL			0x001034
+
+#define IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR	0x400000
+
+#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_ADDR	0x8000
+#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_INC	0x10
+#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL	(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_ADDR)
+
+#define IPQ807X_PPE_L0_FLOW_MAP_TBL_ADDR	0x2000
+#define IPQ807X_PPE_L0_FLOW_MAP_TBL_INC		0x10
+#define IPQ807X_PPE_L0_FLOW_MAP_TBL		(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L0_FLOW_MAP_TBL_ADDR)
+
+#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_ADDR	0x46000
+#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_INC	0x10
+#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL	(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_ADDR)
+
+#define IPQ807X_PPE_L1_FLOW_MAP_TBL_ADDR	0x40000
+#define IPQ807X_PPE_L1_FLOW_MAP_TBL_INC		0x10
+#define IPQ807X_PPE_L1_FLOW_MAP_TBL		(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L1_FLOW_MAP_TBL_ADDR)
+
+#define IPQ807X_PPE_L0_C_SP_CFG_TBL_ADDR	0x4000
+#define IPQ807X_PPE_L0_C_SP_CFG_TBL		(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L0_C_SP_CFG_TBL_ADDR)
+
+#define IPQ807X_PPE_L1_C_SP_CFG_TBL_ADDR	0x42000
+#define IPQ807X_PPE_L1_C_SP_CFG_TBL		(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L1_C_SP_CFG_TBL_ADDR)
+
+#define IPQ807X_PPE_L0_E_SP_CFG_TBL_ADDR	0x6000
+#define IPQ807X_PPE_L0_E_SP_CFG_TBL		(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L0_E_SP_CFG_TBL_ADDR)
+
+#define IPQ807X_PPE_L1_E_SP_CFG_TBL_ADDR		0x44000
+#define IPQ807X_PPE_L1_E_SP_CFG_TBL		(IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ807X_PPE_L1_E_SP_CFG_TBL_ADDR)
+
+#define IPQ807X_PPE_FPGA_GPIO_BASE_ADDR		0x01008000
+
+#define IPQ807X_PPE_MAC_PORT_MUX_OFFSET		0x10
+#define IPQ807X_PPE_FPGA_GPIO_OFFSET		0xc000
+#define IPQ807X_PPE_FPGA_SCHED_OFFSET		0x47a000
+#define IPQ807X_PPE_TDM_CFG_DEPTH_OFFSET	0xb000
+#define IPQ807X_PPE_TDM_SCHED_DEPTH_OFFSET	0x400000
+#define IPQ807X_PPE_PORT_BRIDGE_CTRL_OFFSET	0x060300
+
+#define IPQ807X_PPE_TDM_CFG_DEPTH_VAL		0x80000064
+#define IPQ807X_PPE_MAC_PORT_MUX_OFFSET_VAL	0x15
+#define IPQ807X_PPE_TDM_SCHED_DEPTH_VAL		0x32
+#define IPQ807X_PPE_TDM_CFG_VALID		0x20
+#define IPQ807X_PPE_TDM_CFG_DIR_INGRESS		0x0
+#define IPQ807X_PPE_TDM_CFG_DIR_EGRESS		0x10
+#define IPQ807X_PPE_PORT_EDMA			0x0
+#define IPQ807X_PPE_PORT_QCOM1			0x1
+#define IPQ807X_PPE_PORT_QCOM2			0x2
+#define IPQ807X_PPE_PORT_QCOM3			0x3
+#define IPQ807X_PPE_PORT_QCOM4			0x4
+#define IPQ807X_PPE_PORT_XGMAC1			0x5
+#define IPQ807X_PPE_PORT_XGMAC2			0x6
+#define IPQ807X_PPE_PORT_CRYPTO1		0x7
+#define IPQ807X_PPE_PORT_BRIDGE_CTRL_PROMISC_EN	0x20000
+#define IPQ807X_PPE_PORT_BRIDGE_CTRL_TXMAC_EN	0x10000
+#define IPQ807X_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP	0x7f00
+#define IPQ807X_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN	0x8
+#define IPQ807X_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN	0x1
+
+#define IPQ807X_PPE_PORT_EDMA_BITPOS		0x1
+#define IPQ807X_PPE_PORT_QCOM1_BITPOS		(1 << IPQ807X_PPE_PORT_QCOM1)
+#define IPQ807X_PPE_PORT_QCOM2_BITPOS		(1 << IPQ807X_PPE_PORT_QCOM2)
+#define IPQ807X_PPE_PORT_QCOM3_BITPOS		(1 << IPQ807X_PPE_PORT_QCOM3)
+#define IPQ807X_PPE_PORT_QCOM4_BITPOS		(1 << IPQ807X_PPE_PORT_QCOM4)
+#define IPQ807X_PPE_PORT_XGMAC1_BITPOS		(1 << IPQ807X_PPE_PORT_XGMAC1)
+#define IPQ807X_PPE_PORT_XGMAC2_BITPOS		(1 << IPQ807X_PPE_PORT_XGMAC2)
+#define IPQ807X_PPE_PORT_CRYPTO1_BITPOS		(1 << IPQ807X_PPE_PORT_CRYPTO1)
+

include/configs/ipq807x.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -112,7 +112,7 @@ extern loff_t board_env_offset;
 #define CONFIG_ENV_OFFSET		board_env_offset
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_SIZE_MAX		(256 << 10) /* 256 KB */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE_MAX + (256 << 10))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE_MAX + (512 << 10))
 
 #define CONFIG_ENV_IS_IN_NAND		1
 
@@ -238,6 +238,19 @@ extern loff_t board_env_offset;
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
+#define CONFIG_IPQ807X_EDMA		1
+#define CONFIG_IPQ807X_BRIDGED_MODE	1
+#define CONFIG_NET_RETRY_COUNT		5
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_IPADDR	192.168.10.10
+#define CONFIG_NETMASK	255.255.255.0
+#define CONFIG_SERVERIP	192.168.10.1
+#define CONFIG_CMD_TFTPPUT
+
 /*
  * CRASH DUMP ENABLE
  */