This change will enable page_scope_read & multipage_read support for
QPIC.
QPIC version 2.0 onwards , QPIC support page_scope_read &
multipage_read command to enhance the read performance.
In normal page read command SW is needed to write EXEC_CMD register
for each Code word and collect any Status related to that CW before
issueing EXEC_CMD for next CW.
For page_scope read command SW is required to issue EXEC_CMD
only once for a page. Controller HW takes care of Codeword specific
details and automatically returns status associated with each CW to
BAM pipe, dedicated for status deposition.
enabling all bits in NAND_AUTO_STATUS_EN will require 4 data
descriptors of 24 bytes each. This will publish all NANDc status
registers in system memory.
For multipage_read command SW is required to issue EXEC_CMD only
once for all the pages which configured in QPIC_NAND_MULTI_PAGE_CMD
register.
All interrupts will be operational and valid in these modes.
To check the status for each codeword, it is not possible to access
the status registers while the read command is operational in
page_scope & multi_page read modes. Hence, another feature to publish the
status data (for all NAND status registers) by programming the
NAND_AUTO_STATUS_EN register.
For serial NAND:
Read command for page_scope_read = 0x78800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x78400032 (QPIC_NAND_FLASH_CMD)
For Parallel NAND:
Read command for page_scope_read = 0x00800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x00400032 (QPIC_NAND_FLASH_CMD)
Now we fixed maximum data bytes read in one go 128KiB(2KiB page),
256KiB (4KiB page), 512 KiB (8kiB page), because from upper layer
we are getting more than 128KiB data bytes request in one go. if so
just changing the value of "MAX_MULTI_PAGE" macro will increase the
maximum data bytes in one go.
Change-Id: I48eea51ff8f5f79f3490d8a538c295ecc3eeee19
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Since nand configuration is fixed across all HK boards,
removing the nand gpio_entries from device tree and
adding static board param entries. This helps reduce
image footprint and opens up space for new board support.
Change-Id: I89bc11165a6cdfcdb3b4650a73cbeea17895f991
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Fidelix SPI NAND FM35X2GA has two planes namely plane 0 and plane 1.
This change adds the support to calculate the plane bit accordingly
and use the same for command formation.
Change-Id: I6fb4b652e1c897f248cb9ad8914f67be7a7365f3
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
This change will add support for serial nand.
QPIC-2.1.1 supports parallel nand as well as serial nand.
QPIC will operate either in parallel configuration or
serial nand. Both can't work together.
This change will support initially four serial nand parts.
MT29F1G01ABBFDWB-IT (Micron-0x2C,0x15, 2K + 128)
GD5F1GQ4RE9IG (Giga Device-0xC8,0xC1, 2K + 128)
GD5F2GQ5REYIH (Giga Device-0xC8,0x22, 2K + 64)
GD5F1GQ4RE9IH (Giga Device-0xC8, 0xC9, 2K + 64)
Device Internal ECC is disabled for all three devices. This change will
enabele QPIC ECC engine.
For MT29F1G01ABBFDWB-IT 4-bit ECC as well 8-bit ECC will be supported.
For GD5F1GQ4RE9IG 4-bit ECC as well 8-bit ECC will be supported.
For GD5F2GQ5REYIH only 4-bit ECC will be supported due to 64-bytes spare.
For GD5F1GQ4RE9IH only 4-bit ECC will be supported due to 64-bytes spare.
Change-Id: I3f38f9c76b7bb235bb335a481fbc42ae1bd00395
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This patch fixes the nand flash size access issue
found in flash with two logical units
Change-Id: Ifcbaa40709c4ac5d508b629fcc6cf7006f167628
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This eMMC flash controller support only 4-bit
Update sdhci driver to support 4-bit mode.
Change-Id: Iddaa0807b7cf339fcfa5add0b96955757b33c716
Signed-off-by: Vandhiadevan <vkarunam@codeaurora.org>
This patch adds malloc for loading ethphyfw instead
of loading it in RAM Address.
Change-Id: I0f39d7b61b7675667201a218e5e7830910472b9c
Signed-off-by: speriaka <speriaka@codeaurora.org>
This patch updates the uniphy soft reset function
to do the reset based on uniphy index only for the
required ports.
Change-Id: I7078b7f1e53fd86f32ec213dffe1eeebd5c702ad
Signed-off-by: speriaka <speriaka@codeaurora.org>
Without this change, even during link down, all
the ports were getting configured. This introduces
unnecessary delay.
This patch changes this behaviour and does the
configurations based on link speed, only when link
is up.
Change-Id: Ideed015ab087b317d2617369496c46abf21979f9
Signed-off-by: speriaka <speriaka@codeaurora.org>
This patch adds EDMA HW reset during EDMA init
before disabling interrupts and rings.
Change-Id: I8cf07c0ee35f7efa799037c3b0c22317e248701a
Signed-off-by: speriaka <speriaka@codeaurora.org>
This patch updates the edma eth_recv by disabling
the interrupts for txcmpl and rxfill. These interrupts
are again enabled as and when needed.
This patch also updates the alloc_rx_buffer next
pointer based on currently filled rx buffers.
Change-Id: I84aaba61132d683dc91e8e7156b3919570e4a0d1
Signed-off-by: speriaka <speriaka@codeaurora.org>
This patch removes EDMA config during each ping
and moves it to init code which is executed once
during boot
Change-Id: I0e988ac176386b1b95f1964be02f33a22f8113c3
Signed-off-by: speriaka <speriaka@codeaurora.org>
This patch adds port mac reset during link
speed change.
This patch also adds 100 ms delay after
full reset of NSS PPE and also updates
the comment for gmac disable.
Change-Id: I9c17ff1d0ad47d301094ce06cec07a478f48b1f0
Signed-off-by: speriaka <speriaka@codeaurora.org>
This patch updates the XPCS reset function. It
makes sure only the 2nd bit is modified and not the
entire register. Only 2nd bit needs to be toggled
for XPCS assert and deassert.
Change-Id: I7d11674f253d9b55825d1b285572e824ca218b95
Signed-off-by: speriaka <speriaka@codeaurora.org>
Allow some time for the phy reset to finish and ready for link negotiation.
Change-Id: I72474b7e55ed0d8a091b2b454fe9c3d24c80786b
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
As per the SD controller hardware design document
the SD bus power should be turned off and the iopad
voltage has to be set to 3V (default), before
doing reset for all in SD host controller.
Change-Id: Ia77bb0acefe1e619c8ae7a2bc60024bf1ac5c6cd
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This change will fix the following warning
1.Wint-conversion
Change-Id: Ieb23517197742bd587cc63096477f5e0bacb89c0
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
