mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-02-19 10:41:58 +01:00
ipq5018: Enable support for serial nand in qpic
This change will add support for serial nand. QPIC-2.1.1 supports parallel nand as well as serial nand. QPIC will operate either in parallel configuration or serial nand. Both can't work together. This change will support initially four serial nand parts. MT29F1G01ABBFDWB-IT (Micron-0x2C,0x15, 2K + 128) GD5F1GQ4RE9IG (Giga Device-0xC8,0xC1, 2K + 128) GD5F2GQ5REYIH (Giga Device-0xC8,0x22, 2K + 64) GD5F1GQ4RE9IH (Giga Device-0xC8, 0xC9, 2K + 64) Device Internal ECC is disabled for all three devices. This change will enabele QPIC ECC engine. For MT29F1G01ABBFDWB-IT 4-bit ECC as well 8-bit ECC will be supported. For GD5F1GQ4RE9IG 4-bit ECC as well 8-bit ECC will be supported. For GD5F2GQ5REYIH only 4-bit ECC will be supported due to 64-bytes spare. For GD5F1GQ4RE9IH only 4-bit ECC will be supported due to 64-bytes spare. Change-Id: I3f38f9c76b7bb235bb335a481fbc42ae1bd00395 Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This commit is contained in:
Md Sadre Alam
parent
41a6ccad9e
commit
2c13362d84
7 changed files with 1069 additions and 40 deletions
|
|
@ -28,6 +28,11 @@
|
|||
compatible = "qcom,sdhci-msm";
|
||||
};
|
||||
|
||||
nand: nand-controller@79B0000 {
|
||||
status = "ok";
|
||||
nand_gpio {};
|
||||
};
|
||||
|
||||
timer {
|
||||
gpt_freq_hz = <240000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,4 +64,55 @@
|
|||
spi_gpio {};
|
||||
};
|
||||
|
||||
nand: nand-controller@79B0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,qpic-nand-v2.1.1";
|
||||
reg = <0x79B0000 0x10000>;
|
||||
|
||||
nand_gpio {
|
||||
qspi_data0 {
|
||||
gpio = <7>;
|
||||
func = <2>;
|
||||
pull = <GPIO_PULL_DOWN>;
|
||||
drvstr = <GPIO_8MA>;
|
||||
oe = <GPIO_OE_DISABLE>;
|
||||
};
|
||||
qspi_data1 {
|
||||
gpio = <6>;
|
||||
func = <2>;
|
||||
pull = <GPIO_PULL_DOWN>;
|
||||
drvstr = <GPIO_8MA>;
|
||||
oe = <GPIO_OE_DISABLE>;
|
||||
};
|
||||
qspi_data2 {
|
||||
gpio = <5>;
|
||||
func = <2>;
|
||||
pull = <GPIO_PULL_DOWN>;
|
||||
drvstr = <GPIO_8MA>;
|
||||
oe = <GPIO_OE_DISABLE>;
|
||||
};
|
||||
qspi_data3 {
|
||||
gpio = <4>;
|
||||
func = <2>;
|
||||
pull = <GPIO_PULL_DOWN>;
|
||||
drvstr = <GPIO_8MA>;
|
||||
oe = <GPIO_OE_DISABLE>;
|
||||
};
|
||||
qspi_cs_n {
|
||||
gpio = <8>;
|
||||
func = <2>;
|
||||
pull = <GPIO_PULL_DOWN>;
|
||||
drvstr = <GPIO_8MA>;
|
||||
oe = <GPIO_OE_DISABLE>;
|
||||
};
|
||||
qspi_clk {
|
||||
gpio = <9>;
|
||||
func = <2>;
|
||||
pull = <GPIO_PULL_DOWN>;
|
||||
drvstr = <GPIO_8MA>;
|
||||
oe = <GPIO_OE_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -94,11 +94,200 @@
|
|||
#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
|
||||
#define NAND_HW_INFO NAND_REG(0x00FC)
|
||||
#define NAND_FLASH_BUFFER NAND_REG(0x0100)
|
||||
#define NAND_FLASH_FEATURES NAND_REG(0x0F64)
|
||||
#define QPIC_NAND_CTRL NAND_REG(0x0F00)
|
||||
#define QPIC_NAND_DEBUG NAND_REG(0x0F0C)
|
||||
/* Additional Register set for Serial NAND */
|
||||
#define NAND_AUTO_STATUS_EN NAND_REG(0x002C)
|
||||
#define NAND_VERSION NAND_REG(0x4F08)
|
||||
#define SPI_NAND_DEV_CMD0 NAND_REG(0x70A0)
|
||||
#define SPI_NAND_DEV_CMD1 NAND_REG(0x70A4)
|
||||
#define SPI_NAND_DEV_CMD2 NAND_REG(0x70A8)
|
||||
#define SPI_NAND_DEV_CMD3 NAND_REG(0x70D0)
|
||||
#define NAND_FLASH_DEV_CMD_VLD NAND_REG(0x70AC)
|
||||
#define SPI_NAND_DEV_CMD7 NAND_REG(0x70B0)
|
||||
#define SPI_NAND_DEV_CMD8 NAND_REG(0x70B4)
|
||||
#define SPI_NAND_DEV_CMD9 NAND_REG(0x70B8)
|
||||
#define NAND_FLASH_SPI_CFG NAND_REG(0x70C0)
|
||||
#define NAND_SPI_NUM_ADDR_CYCLES NAND_REG(0x70C4)
|
||||
#define NAND_SPI_BUSY_CHECK_WAIT_CNT NAND_REG(0x70C8)
|
||||
|
||||
/* Register mask & shift value used in SPI transfer mode */
|
||||
#define SPI_TRANSFER_MODE_1X 0x1
|
||||
#define SPI_TRANSFER_MODE_4X 0x3
|
||||
/* These value as per HPG , these value as per 2K device*/
|
||||
#define SPI_NAND_DEVn_CFG0 0x1A5408D0
|
||||
#define SPI_NAND_DEVn_CFG1 0x08287440
|
||||
#define SPI_NAND_DEVn_CFG1_RESET 0x087476B1
|
||||
/* value for below register according to HPG : 0x42040702 for reset
|
||||
* and 0x42040700 for reset disable
|
||||
*/
|
||||
#define SPI_NAND_DEVn_ECC_CFG 0x42040702
|
||||
#define SPI_NAND_DEVn_ECC_CFG_RST_DIS 0x42040700
|
||||
#define FLASH_DEV_CMD_VLD 0x0000000D
|
||||
/* These Value as per HPG */
|
||||
#define NAND_FLASH_DEV_CMD0_VAL 0x1080D8D8
|
||||
#define NAND_FLASH_DEV_CMD1_VAL 0xF00F3000
|
||||
#define NAND_FLASH_DEV_CMD2_VAL 0xF0FF709F
|
||||
#define NAND_FLASH_DEV_CMD3_VAL 0x3F310015
|
||||
/* For Micron NAND_FLASH_DEV_CMD3_VAL value should
|
||||
* be 0x3F300015
|
||||
*/
|
||||
#define NAND_FLASH_DEV_CMD7_VAL 0x04061F0F
|
||||
#define NAND_FLASH_DEV_CMD7_WE 0x60000
|
||||
#define NAND_FLASH_DEV_CMD7_WD 0x40000000
|
||||
#define NAND_FLASH_DEV_CMD7_SET_FTR 0x1F00
|
||||
#define NAND_FLASH_DEV_CMD7_GET_FTR 0x0F
|
||||
#define SPI_BUSY_CHECK_WAIT_CNT 0x00000010
|
||||
#define SPI_CFG_VAL 0x1924C00D
|
||||
#define SPI_LOAD_CLK_CNTR_INIT_EN (1 << 28)
|
||||
#define SPI_NUM_ADDR_CYCLES 0x000DA4DB
|
||||
#define NAND_FLASH_SET_FEATURE_MASK 0xB800000E
|
||||
#define NAND_FLASH_GET_FEATURE_MASK 0x3800000E
|
||||
#define QPIC_HARDWARE_VERSION_2_0 0x20000000
|
||||
#define NAND_FLASH_STATUS_MASK 0xC
|
||||
#define QPIC_SERIAL_ERROR 517
|
||||
#define QPIC_SPI_SET_FEATURE (1 << 31)
|
||||
#define QPIC_SPI_GET_FEATURE ~(1 << 31)
|
||||
#define QPIC_SPI_WP_SET (1 << 28)
|
||||
#define QPIC_SPI_HOLD_SET (1 << 27)
|
||||
#define QPIC_SPI_TRANSFER_MODE_X1 (1 << 29)
|
||||
#define QPIC_SPI_TRANSFER_MODE_X4 (3 << 29)
|
||||
#define QPIC_SPI_BOOST_MODE (1 << 11)
|
||||
#define QPIC_SPI_NAND_CTRL_VAL 0x341
|
||||
#define QPIC_SPI_NAND_AUTO_STATUS_VAL 0x003F003F
|
||||
#define QPIC_NAND_FLASH_CMD_WE_VAL 0XB800000F
|
||||
#define QPIC_NAND_FLASH_CMD_WD_VAL 0x3800000F
|
||||
#define WR_EN 0x1
|
||||
#define WR_DIS 0x0
|
||||
|
||||
/* According to GigaDevice data sheet Block Protection Register is:
|
||||
* ____________________________________________
|
||||
* | | | | | | | | |
|
||||
* |BRWD |RSVD| BP2| BP1| BP0| INV | CMP |RSVD |
|
||||
* | | | | | | | | |
|
||||
* |______|____|____|____|____|_____|_____|_____|
|
||||
*
|
||||
* NOTE: RSVD = Reserved.
|
||||
*
|
||||
* After power-up the device is in "locked" state i.e feature bits
|
||||
* BP0, BP1, BP2 are set to 1. ENV, CMP, BRWD are set to 0.
|
||||
* When BRWD is set to 1 and WP# is LOW i.e 0, none of the writable
|
||||
* protection feature bits can be set.
|
||||
* When an ERASE command is issued to a locked block, the erase failure,
|
||||
* 04H, is returned.
|
||||
*
|
||||
* With CMP = X, INV = X, BP2 = 0, BP1 = 0, BP0 = 0 : There will be no
|
||||
* block protection functionality.
|
||||
*
|
||||
* When WP# is not LOW, user can issue bellows commands to alter the
|
||||
* protection.
|
||||
*
|
||||
* Issue SET FEATURES register write (1FH)
|
||||
* Issue the feature bit address (A0h)
|
||||
*/
|
||||
#define FLASH_SPI_NAND_BLK_PROCT_ADDR 0xA0
|
||||
#define FLASH_SPI_NAND_BLK_PROCT_DISABLE 0x00
|
||||
#define FLASH_SPI_NAND_BLK_PROCT_ENABLE 0x78
|
||||
/* According to GigaDevice data sheet Feature Register is:
|
||||
* _________________________________________________
|
||||
* | | | | | | | | |
|
||||
* |OTP-PRT|OTP_EN| RSVD|ECC-EN|RSVD|RSVD |RSVD |QE |
|
||||
* | | | | | | | | |
|
||||
* |_______|______|_____|______|____|_____|_____|____|
|
||||
*
|
||||
*
|
||||
* NOTE : When a feature is set, it remains active until the
|
||||
* device is power cycled or the feature is written to.once
|
||||
* the device is set, it remains set, even if a RESET (FFH)
|
||||
* command is issued.
|
||||
*
|
||||
* OTP-PRT = X , OTP_EN = 0 : Normal Operation
|
||||
* OTP-PRT = 0, OTP_EN = 1 : Access OTP region, read and program data.
|
||||
*
|
||||
* ECC-EN : ECC is enabled after device power up, so the default
|
||||
* READ and PROGRAM commands operate with internal ECC in the “active”
|
||||
* state. To enable/disable ECC, perform the following command sequence:
|
||||
*
|
||||
* 1) Issue the SET FEATURES command (1FH).
|
||||
* 2) Set the feature bit ECC_EN as you want:
|
||||
* a) To enable ECC, Set ECC_EN to 1.
|
||||
* b) To disable ECC, Clear ECC_EN to 0.
|
||||
*
|
||||
* NOTE: For this device GD5F1GQ4xExxG
|
||||
* --> Internal ECC Off (ECC_EN=0):
|
||||
* 2048-Byte+128-Byte Full Access.
|
||||
*
|
||||
* --> Internal ECC On (ECC_EN=1, default):
|
||||
* Program: 2048-Byte+64-Byte.
|
||||
* Read: 2048-Byte+128-Byte.
|
||||
*
|
||||
* QE : If QE is enabled, the quad IO operations can be executed.
|
||||
*
|
||||
*/
|
||||
#define FLASH_SPI_NAND_FR_ADDR 0xB0
|
||||
#define FLASH_SPI_NAND_FR_ECC_ENABLE (1 << 4)
|
||||
#define FLASH_SPI_NAND_FR_QUAD_ENABLE 0x1
|
||||
/* According to GigaDevice data sheet Status Register(0xC0) is:
|
||||
* _________________________________________________
|
||||
* | | | | | | | | |
|
||||
* |RSVD |RSVD |ECCS1|ECCS0|P-FAIL|E-FAIL|WEL |OIP |
|
||||
* | | | | | | | | |
|
||||
* |______|______|_____|_____|_____ |______|____|____|
|
||||
*
|
||||
*
|
||||
* NOTE: RSVD = Reserved.
|
||||
*
|
||||
* P-FAIL : This bit indicates that a program failure has occurred
|
||||
* (P_FAIL set to 1). It will also be set if the user attempts to
|
||||
* program an invalid address or a protected region, including
|
||||
* the OTP area.
|
||||
*
|
||||
* E-FAIL : This bit indicates that an erase failure has occurred
|
||||
* (E_FAIL set to 1). It will also be set if the user attempts to
|
||||
* erase a locked region.
|
||||
*
|
||||
* WEL : This bit indicates the current status of the write enable
|
||||
* latch (WEL) and must be set (WEL = 1), prior to issuing a
|
||||
* PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the
|
||||
* WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing
|
||||
* the WRITE DISABLE command.
|
||||
*
|
||||
* OIP : This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ,
|
||||
* BLOCK ERASE, or RESET command is executing, indicating the device
|
||||
* is busy. When the bit is 0, the interface is in the ready state.
|
||||
*
|
||||
* ECC Status : ECCS and ECCSE are set to 00b either following a RESET,
|
||||
* or at the beginning of the READ.ECCS and ECCSE are invalid if internal
|
||||
* ECC is disabled (via a SET FEATURES command to reset ECC_EN to 0).
|
||||
*
|
||||
* NOTE: After power-on RESET, ECC status is set to reflect the contents
|
||||
* of block 0, page 0.
|
||||
*/
|
||||
#define FLASH_SPI_NAND_SR_ADDR 0xC0
|
||||
#define FLASH_SPI_NAND_SR_DATA 0x00
|
||||
|
||||
/* According to GigaDevice data sheet Feature Register(0xD0) is:
|
||||
* _________________________________________________
|
||||
* | | | | | | | | |
|
||||
* |RSVD |DS-S1|DS-S0|RSVD |RSVD |RSVD |RSVD |RSVD|
|
||||
* | | | | | | | | |
|
||||
* |______|_____|_____|_____|______|______|_____|____|
|
||||
*
|
||||
* DS-S1 = 0 , DS-S0 = 0 : Drive strength is 50%
|
||||
* DS-S1 = 0 , DS-S0 = 1 : Drive strength is 25%
|
||||
* DS-S1 = 1 , DS-S0 = 0 : Drive strength is 75%
|
||||
* DS-S1 = 1 , DS-S0 = 1 : Drive strength is 100%
|
||||
*
|
||||
* 00 is the default data byte value for Output Driver Register after power-up
|
||||
*/
|
||||
#define FLASH_SPI_NAND_FR_DS_ADDR 0xD0
|
||||
#define FLASH_SPI_NAND_FR_DS_DATA 0x00
|
||||
|
||||
|
||||
/* NANDc registers used during BAM transfer */
|
||||
#define NAND_READ_LOCATION_n(n) (NAND_REG(0xF20) + 4 * (n))
|
||||
#define NAND_READ_LOCATION_LAST_CW_n(n) (NAND_REG(0xF40) + 4 * (n))
|
||||
#define NAND_RD_LOC_LAST_BIT(x) ((x) << 31)
|
||||
#define NAND_RD_LOC_SIZE(x) ((x) << 16)
|
||||
#define NAND_RD_LOC_OFFSET(x) ((x) << 0)
|
||||
|
|
@ -151,6 +340,23 @@
|
|||
#define NAND_CMD_BLOCK_ERASE 0x3A
|
||||
#define NAND_CMD_FETCH_ID 0x0B
|
||||
#define NAND_CMD_RESET_DEVICE 0x0D
|
||||
#define NAND_CMD_SET_FEATURE 0x1F
|
||||
#define NAND_CMD_GET_FEATURE 0x0F
|
||||
#define NAND_CMD_ACC_FEATURE 0x0E
|
||||
/* Serial NAND Device command */
|
||||
#define SERIAL_NAND_CMD_READ_FROM_CACHE_X4 0x6B
|
||||
#define SERIAL_NAND_CMD_READ_FROM_CACHE_DUAL_IO 0xBB
|
||||
#define SERIAL_NAND_CMD_READ_FROM_CACHE_QUAD_IO 0xEB
|
||||
#define SERIAL_NAND_CMD_READ_ID 0x9F
|
||||
#define SERIAL_NAND_CMD_PROGRAM_LOAD 0x02
|
||||
#define SERIAL_NAND_CMD_PROGRAM_LOAD_X4 0x32
|
||||
#define SERIAL_NAND_CMD_PROGRAM_EXECUTE 0x10
|
||||
#define SERIAL_NAND_CMD_PROGRAM_LOAD_RND_DATA 0x84
|
||||
#define SERIAL_NAND_CMD_PROGRAM_LOAD_RND_DATA_X4 0xC4 /* Or 0x34 */
|
||||
#define SERIAL_NAND_CMD_PROGRAM_LOAD_QUAD_IO 0x72
|
||||
#define SERIAL_NAND_CMD_BLOCK_ERASE 0xD8
|
||||
#define SERIAL_NAND_CMD_RESET 0xFF
|
||||
|
||||
/* NAND Status errors */
|
||||
#define NAND_FLASH_MPU_ERR (1 << 8)
|
||||
#define NAND_FLASH_TIMEOUT_ERR (1 << 6)
|
||||
|
|
@ -170,6 +376,7 @@
|
|||
#define DATA_CONSUMER_PIPE_INDEX 0
|
||||
#define DATA_PRODUCER_PIPE_INDEX 1
|
||||
#define CMD_PIPE_INDEX 2
|
||||
#define BAM_STATUS_PIPE_INDEX 3
|
||||
|
||||
/* Define BAM pipe lock groups for NANDc*/
|
||||
#define P_LOCK_GROUP_0 0
|
||||
|
|
@ -238,11 +445,13 @@
|
|||
#define DATA_CONSUMER_PIPE 0
|
||||
#define DATA_PRODUCER_PIPE 1
|
||||
#define CMD_PIPE 2
|
||||
#define NAND_BAM_STATUS_PIPE 3
|
||||
|
||||
/* NANDc BAM pipe groups */
|
||||
#define DATA_PRODUCER_PIPE_GRP 0
|
||||
#define DATA_CONSUMER_PIPE_GRP 0
|
||||
#define CMD_PIPE_GRP 1
|
||||
#define NAND_BAM_STATUS_PIPE_GRP 2
|
||||
|
||||
/* NANDc EE */
|
||||
#define QPIC_NAND_EE 0
|
||||
|
|
@ -252,6 +461,7 @@
|
|||
|
||||
/* Register: NAND_CTRL */
|
||||
#define BAM_MODE_EN 0x1
|
||||
#define NANDC_READ_DELAY_COUNTER_VAL 0x340
|
||||
|
||||
/* Register: NAND_DEBUG */
|
||||
#define BAM_MODE_BIT_RESET (1 << 31)
|
||||
|
|
@ -277,6 +487,7 @@
|
|||
|
||||
#define QPIC_BAM_DATA_FIFO_SIZE 64
|
||||
#define QPIC_BAM_CMD_FIFO_SIZE 64
|
||||
#define QPIC_BAM_STATUS_FIFO_SIZE 64
|
||||
|
||||
#define QPIC_MAX_ONFI_MODES 4
|
||||
#define QPIC_NUM_XFER_STEPS 7
|
||||
|
|
@ -284,7 +495,7 @@
|
|||
enum qpic_verion{
|
||||
QCA_QPIC_V1_4_20,
|
||||
QCA_QPIC_V1_5_20,
|
||||
|
||||
QCA_QPIC_V2_1_1,
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -311,6 +522,28 @@ enum nand_cfg_value
|
|||
NAND_CFG,
|
||||
};
|
||||
|
||||
/* Structure for Serial nand parameter */
|
||||
struct qpic_serial_nand_params {
|
||||
u8 id[4];
|
||||
u16 page_size;
|
||||
u16 pgs_per_blk;
|
||||
u32 spare_size;
|
||||
u32 erase_blk_size;
|
||||
u16 no_of_blocks;
|
||||
u32 density;
|
||||
u32 otp_region;
|
||||
u8 no_of_addr_cycle;
|
||||
u8 no_of_dies;
|
||||
u8 num_bits_ecc_correctability;
|
||||
u8 timing_mode_support;
|
||||
bool quad_mode;
|
||||
bool check_quad_config;
|
||||
int prev_die_id;
|
||||
u8 protec_bpx;
|
||||
u64 pages_per_die;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
struct onfi_param_page
|
||||
{
|
||||
uint32_t signature;
|
||||
|
|
@ -396,9 +629,15 @@ struct qpic_nand_bam_pipes
|
|||
unsigned read_pipe;
|
||||
unsigned write_pipe;
|
||||
unsigned cmd_pipe;
|
||||
#if defined(QPIC_SERIAL) && defined(MULTI_PAGE_READ)
|
||||
unsigned status_pipe;
|
||||
#endif
|
||||
uint8_t read_pipe_grp;
|
||||
uint8_t write_pipe_grp;
|
||||
uint8_t cmd_pipe_grp;
|
||||
#if defined(QPIC_SERIAL) && defined(MULTI_PAGE_READ)
|
||||
uint8_t status_pipe_grp;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Structure to define the initial nand config */
|
||||
|
|
@ -442,6 +681,10 @@ struct qpic_nand_dev {
|
|||
uint32_t cfg0_raw;
|
||||
uint32_t cfg1_raw;
|
||||
uint32_t ecc_bch_cfg;
|
||||
#ifdef CONFIG_QPIC_SERIAL
|
||||
bool quad_mode;
|
||||
bool check_quad_config;
|
||||
#endif
|
||||
unsigned oob_per_page;
|
||||
unsigned char *buffers;
|
||||
unsigned char *pad_dat;
|
||||
|
|
|
|||
|
|
@ -290,8 +290,17 @@ void reset_crashdump(void)
|
|||
return;
|
||||
}
|
||||
|
||||
void qpic_clk_enbale(void)
|
||||
{
|
||||
writel(QPIC_CBCR_VAL, GCC_QPIC_CBCR_ADDR);
|
||||
writel(0x1, GCC_QPIC_AHB_CBCR_ADDR);
|
||||
writel(0x1, GCC_QPIC_IO_MACRO_CBCR);
|
||||
}
|
||||
|
||||
void board_nand_init(void)
|
||||
{
|
||||
qpic_nand_init();
|
||||
|
||||
#ifdef CONFIG_QCA_SPI
|
||||
int gpio_node;
|
||||
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
|
||||
|
|
|
|||
|
|
@ -35,6 +35,15 @@
|
|||
#define GCC_SDCC1_AHB_CBCR 0x0184201C
|
||||
#define GCC_SDCC1_MISC 0x01842020
|
||||
|
||||
/*
|
||||
* GCC-QPIC Registers
|
||||
*/
|
||||
#define GCC_QPIC_IO_MACRO_CBCR 0x0185701C
|
||||
#define GCC_QPIC_CBCR_ADDR 0x01857020
|
||||
#define GCC_QPIC_AHB_CBCR_ADDR 0x01857024
|
||||
#define GCC_QPIC_SLEEP_CBCR 0x01857028
|
||||
#define QPIC_CBCR_VAL 0x80004FF1
|
||||
|
||||
/* UART 1 */
|
||||
#define GCC_BLSP1_UART1_BCR 0x01802038
|
||||
#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203C
|
||||
|
|
@ -118,6 +127,7 @@ struct smem_ram_ptable {
|
|||
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
|
||||
void reset_crashdump(void);
|
||||
void reset_board(void);
|
||||
void qpic_clk_enbale(void);
|
||||
|
||||
typedef enum {
|
||||
SMEM_SPINLOCK_ARRAY = 7,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -130,6 +130,10 @@ extern loff_t board_env_size;
|
|||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* QSPI Flash configs
|
||||
*/
|
||||
#define CONFIG_QPIC_SERIAL
|
||||
|
||||
/*
|
||||
* SPI Flash Configs
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue