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ipq5018: Add Pcie support

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Change-Id: Ifcb632b0cda947002e0538778484bb866f8227f8
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
This commit is contained in:
Vandhiadevan Karunamoorthy 2020-02-06 12:15:48 +05:30 • committed by Gerrit - the friendly Code Review server
parent bbbdb8e5ab
commit 3f50b516ff
7 changed files with 227 additions and 16 deletions
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1
arch/arm/dts/ipq5018-emulation.dts
View file

@ -25,6 +25,7 @@
i2c0 = "/i2c@78b6000";
gmac_gpio = "/gmac_gpio";
usb0 = "/xhci@8a00000";
pci0 = "/pci@80000000";
};
mmc: sdhci@7804000 {

100
arch/arm/dts/ipq5018-soc.dtsi
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -148,4 +148,102 @@
reg = <0x8a00000 0xe000>;
};
pci@80000000 {
compatible = "qcom,ipq5018-pcie";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0xf1d
0x78000 0x3000
0x80000F20 0xa8
0x80001000 0x1000
0x80300000 0xd00000
0x80100000 0x100000
0x01875004 0x40
0x84000 0x1000>;
reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
"axi_conf", "pci_rst", "pci_phy";
perst_gpio = <27>;
gen3 = <1>;
pci_gpio {
gpio1 {
gpio = <14>;
func = <0>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES0>;
};
gpio2 {
gpio = <15>;
func = <0>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES0>;
};
gpio3 {
gpio = <16>;
func = <0>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES0>;
};
gpio4 {
gpio = <27>;
func = <0>;
out = <GPIO_OUT_HIGH>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES0>;
};
};
};
pci@a0000000 {
compatible = "qcom,ipq5018-pcie";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xa0000000 0xf1d
0x80000 0x3000
0xa0000F20 0xa8
0xa0001000 0x1000
0xa0300000 0xd00000
0xa0100000 0x100000
0x01875004 0x40
0x84000 0x1000>;
reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
"axi_conf", "pci_rst", "pci_phy";
perst_gpio = <28>;
gen3 = <1>;
pci_gpio {
gpio1 {
gpio = <17>;
func = <0>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES0>;
};
gpio2 {
gpio = <28>;
func = <0>;
out = <GPIO_OUT_HIGH>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES0>;
};
};
};
};

55
board/qca/arm/ipq5018/ipq5018.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -839,3 +839,56 @@ int ipq_board_usb_init(void)
}
#endif
#ifdef CONFIG_PCI_IPQ
void board_pci_init(int id)
{
int node, gpio_node;
char name[16];
snprintf(name, sizeof(name), "pci%d", id);
node = fdt_path_offset(gd->fdt_blob, name);
if (node < 0) {
printf("Could not find PCI in device tree\n");
return;
}
gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "pci_gpio");
if (gpio_node >= 0)
qca_gpio_init(gpio_node);
return;
}
void board_pci_deinit()
{
int node, gpio_node, i, err;
char name[16];
struct fdt_resource parf;
struct fdt_resource pci_phy;
for (i = 0; i < PCI_MAX_DEVICES; i++) {
snprintf(name, sizeof(name), "pci%d", i);
node = fdt_path_offset(gd->fdt_blob, name);
if (node < 0) {
printf("Could not find PCI in device tree\n");
return;
}
err = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", "parf",
&parf);
writel(0x0, parf.start + 0x358);
writel(0x1, parf.start + 0x40);
err = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", "pci_phy",
&pci_phy);
if (err < 0)
return;
writel(0x1, pci_phy.start + 800);
writel(0x0, pci_phy.start + 804);
gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "pci_gpio");
if (gpio_node >= 0)
qca_gpio_deinit(gpio_node);
}
return ;
}
#endif

48
board/qca/arm/ipq5018/ipq5018.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -235,6 +235,48 @@
setbits_le32(addr, value); \
mdelay(delay); \
clrbits_le32(addr, value); \
/*
* PCIE Register
*/
#define GCC_SYS_NOC_PCIE0_AXI_CBCR 0x01826048
#define GCC_SYS_NOC_PCIE1_AXI_CBCR 0x0182604C
#define GCC_PCIE0_BOOT_CLOCK_CTL 0x01875000
#define GCC_PCIE0_BCR 0x01875004
#define GCC_PCIE0_AXI_M_CBCR 0x01875008
#define GCC_PCIE0_AXI_S_CBCR 0x0187500C
#define GCC_PCIE0_AHB_CBCR 0x01875010
#define GCC_PCIE0_PHY_PIPE_MISC 0x0187501C
#define GCC_PCIE0_AUX_CBCR 0x01875014
#define GCC_PCIE0_PIPE_CBCR 0x01875018
#define GCC_PCIE0_PHY_PIPE_MISC 0x0187501C
#define GCC_PCIE0_AUX_CMD_RCGR 0x01875020
#define GCC_PCIE0_AUX_CFG_RCGR 0x01875024
#define GCC_PCIE0_PHY_BCR 0x01875038
#define GCC_PCIE0PHY_PHY_BCR 0x0187503C
#define GCC_PCIE0_MISC_RESET 0x01875040
#define GCC_PCIE0_AXI_S_BRIDGE_CBCR 0x01875048
#define GCC_PCIE0_AXI_CMD_RCGR 0x01875050
#define GCC_PCIE0_AXI_CFG_RCGR 0x01875054
#define GCC_PCIE0_LINK_DOWN_BCR 0x018750A8
#define GCC_PCIE1_BOOT_CLOCK_CTL 0x01876000
#define GCC_PCIE1_BCR 0x01876004
#define GCC_PCIE1_AXI_M_CBCR 0x01876008
#define GCC_PCIE1_AXI_S_CBCR 0x0187600C
#define GCC_PCIE1_AHB_CBCR 0x01876010
#define GCC_PCIE1_AUX_CBCR 0x01876014
#define GCC_PCIE1_PIPE_CBCR 0x01876018
#define GCC_PCIE1_PHY_PIPE_MISC 0x0187601C
#define GCC_PCIE1_AUX_CMD_RCGR 0x01876020
#define GCC_PCIE1_AUX_CFG_RCGR 0x01876024
#define GCC_PCIE1_PHY_BCR 0x01876038
#define GCC_PCIE1PHY_PHY_BCR 0x0187603C
#define GCC_PCIE1_MISC_RESET 0x01876040
#define GCC_PCIE1_LINK_DOWN_BCR 0x01876044
#define GCC_PCIE1_AXI_S_BRIDGE_CBCR 0x01876048
#define GCC_PCIE1_AXI_CMD_RCGR 0x01876050
#define GCC_PCIE1_AXI_CFG_RCGR 0x01876054
#define NOT_2D(two_d) (~two_d)
#define NOT_N_MINUS_M(n,m) (~(n - m))
@ -276,6 +318,10 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
extern void ipq_gmac_common_init(ipq_gmac_board_cfg_t *cfg);
extern int ipq_gmac_init(ipq_gmac_board_cfg_t *cfg);
#ifdef CONFIG_PCI_IPQ
void board_pci_init(int id);
#endif
struct smem_ram_ptn {
char name[16];
unsigned long long start;

1
configs/ipq5018_defconfig
View file

@ -219,6 +219,7 @@ CONFIG_SIMPLE_BUS=y
# PCI
#
# CONFIG_DM_PCI is not set
CONFIG_PCI_IPQ=y
#
# Pin controllers

27
drivers/pci/pci_ipq.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, 2015-2017 The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2015-2017, 2020 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -606,6 +606,7 @@ static const struct udevice_id pcie_ver_ids[] = {
{ .compatible = "qcom,ipq40xx-pcie", .data = PCIE_V1 },
{ .compatible = "qcom,ipq807x-pcie", .data = PCIE_V2 },
{ .compatible = "qcom,ipq6018-pcie", .data = PCIE_V2 },
{ .compatible = "qcom,ipq5018-pcie", .data = PCIE_V2 },
{ },
};
@ -927,7 +928,6 @@ void pcie_linkup(struct ipq_pcie *pcie)
writel(val, pcie->pci_dbi.start + PCIE_0_GEN2_CTRL_REG);
writel(PCI_TYPE0_BUS_MASTER_EN,
pcie->pci_dbi.start + PCIE_0_TYPE0_STATUS_COMMAND_REG_1);
writel(DBI_RO_WR_EN, pcie->pci_dbi.start + PCIE_0_MISC_CONTROL_1_REG);
writel(0x0002FD7F, pcie->pci_dbi.start + 0x84);
@ -963,18 +963,19 @@ void pcie_linkup(struct ipq_pcie *pcie)
}
udelay(100);
}
if (pcie->is_gen3) {
writel(0x20001000, pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_BASE);
writel(0x20100000, pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_LIMIT);
writel(0x20001000, pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_BASE);
writel(0x20100000, pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_LIMIT);
writel(0x20000000, pcie->parf.start + PARF_ECAM_BASE);
writel(0x20001000, pcie->parf.start + PARF_ECAM_OFFSET_REMOVAL_BASE);
writel(0x20200000, pcie->parf.start + PARF_ECAM_OFFSET_REMOVAL_LIMIT);
writel(0x20108000, pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_BASE_2);
writel(0x20200000, pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_LIMIT_2);
writel(0x20108000, pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_BASE_2);
writel(0x20200000, pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_LIMIT_2);
writel((pcie->pci_dbi.start + 0x1000), pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_BASE);
writel((pcie->pci_dbi.start + 0x100000), pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_LIMIT);
writel((pcie->pci_dbi.start + 0x1000), pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_BASE);
writel((pcie->pci_dbi.start + 0x100000), pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_LIMIT);
writel((pcie->pci_dbi.start), pcie->parf.start + PARF_ECAM_BASE);
writel((pcie->pci_dbi.start + 0x1000), pcie->parf.start + PARF_ECAM_OFFSET_REMOVAL_BASE);
writel((pcie->pci_dbi.start + 0x200000), pcie->parf.start + PARF_ECAM_OFFSET_REMOVAL_LIMIT);
writel((pcie->pci_dbi.start + 0x108000), pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_BASE_2);
writel((pcie->pci_dbi.start + 0x200000), pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_LIMIT_2);
writel((pcie->pci_dbi.start + 0x108000), pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_BASE_2);
writel((pcie->pci_dbi.start + 0x200000), pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_LIMIT_2);
ipq_pcie_prog_outbound_atu(pcie);
} else {
ipq_pcie_config_controller(pcie);

11
include/configs/ipq5018.h
View file

@ -18,6 +18,7 @@
#include <generated/asm-offsets.h>
#endif
#define IPQ5018_EMULATION
#define CONFIG_IPQ5018
#undef CONFIG_QCA_DISABLE_SCM
#define CONFIG_SPI_FLASH_CYPRESS
@ -237,6 +238,16 @@ extern loff_t board_env_size;
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
/*
* PCIE Enable
*/
#define PCI_MAX_DEVICES 1
#if defined(CONFIG_PCI_IPQ) && !defined(IPQ5018_EMULATION)
#define CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
/*
* Expose SPI driver as a pseudo NAND driver to make use
* of U-Boot's MTD framework.