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u-boot: ipq6018: Fix i2c and net driver compile time warnings

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Change-Id: I269d0bd681d2a9e4042eb3943b0060e36d9b3758
Signed-off-by: speriaka <speriaka@codeaurora.org>
This commit is contained in:
speriaka 2019-06-18 17:16:09 +05:30 • committed by Gerrit - the friendly Code Review server
parent c7bd644365
commit 643b6d5eb5
3 changed files with 4 additions and 100 deletions
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4
arch/arm/include/asm/arch-qca-common/qca_common.h
View file

@ -16,6 +16,10 @@
#include <asm/u-boot.h>
#include <asm/arch-qca-common/smem.h>
#ifdef CONFIG_ARCH_IPQ6018
#include <asm/arch-ipq6018/clk.h>
#endif
#ifdef CONFIG_ARCH_IPQ807x
#include <asm/arch-ipq807x/clk.h>
#endif

96
board/qca/arm/ipq6018/ipq6018.h
View file

@ -27,102 +27,6 @@
#define PPE_ASSERT 0xf0000
#define PPE_DEASSERT 0x0
/*
* GCC_NSS_RCGR Registers
*/
#define GCC_NSS_PORT1_RX_CFG_RCGR 0x01868024
#define GCC_NSS_PORT1_RX_CMD_RCGR 0x01868020
#define GCC_NSS_PORT1_TX_CFG_RCGR 0x0186802C
#define GCC_NSS_PORT1_TX_CMD_RCGR 0x01868028
#define GCC_NSS_PORT2_RX_CFG_RCGR 0x01868034
#define GCC_NSS_PORT2_RX_CMD_RCGR 0x01868030
#define GCC_NSS_PORT2_TX_CFG_RCGR 0x0186803C
#define GCC_NSS_PORT2_TX_CMD_RCGR 0x01868038
#define GCC_NSS_PORT3_RX_CFG_RCGR 0x01868044
#define GCC_NSS_PORT3_RX_CMD_RCGR 0x01868040
#define GCC_NSS_PORT3_TX_CFG_RCGR 0x0186804C
#define GCC_NSS_PORT3_TX_CMD_RCGR 0x01868048
#define GCC_NSS_PORT4_RX_CFG_RCGR 0x01868054
#define GCC_NSS_PORT4_RX_CMD_RCGR 0x01868050
#define GCC_NSS_PORT4_TX_CFG_RCGR 0x0186805C
#define GCC_NSS_PORT4_TX_CMD_RCGR 0x01868058
#define GCC_NSS_PORT5_RX_CFG_RCGR 0x01868064
#define GCC_NSS_PORT5_RX_CMD_RCGR 0x01868060
#define GCC_NSS_PORT5_TX_CFG_RCGR 0x0186806C
#define GCC_NSS_PORT5_TX_CMD_RCGR 0x01868068
#define GCC_NSS_PPE_CFG_RCGR 0x01868084
#define GCC_NSS_PPE_CMD_RCGR 0x01868080
#define GCC_NSS_CRYPTO_CMD_RCGR 0x01868144
#define GCC_NSS_CRYPTO_CFG_RCGR 0x01868148
#define GCC_SNOC_NSSNOC_BFDCD_CMD_RCGR 0x01876054
#define GCC_SNOC_NSSNOC_BFDCD_CFG_RCGR 0x01876058
#define GCC_QDSS_AT_CMD_RCGR 0x0182900C
#define GCC_QDSS_AT_CFG_RCGR 0x01829010
#define GCC_NSS_CE_CMD_RCGR 0x01868098
#define GCC_NSS_CE_CFG_RCGR 0x0186809C
#define GCC_PCNOC_BFDCD_CMD_RCGR 0x01827000
#define GCC_PCNOC_BFDCD_CFG_RCGR 0x01827004
/*
* GCC_NSS_CBCR Registers
*/
#define GCC_NSS_PORT1_RX_CBCR 0x01868240
#define GCC_NSS_PORT1_TX_CBCR 0x01868244
#define GCC_NSS_PORT2_RX_CBCR 0x01868248
#define GCC_NSS_PORT2_TX_CBCR 0x0186824C
#define GCC_NSS_PORT3_RX_CBCR 0x01868250
#define GCC_NSS_PORT3_TX_CBCR 0x01868254
#define GCC_NSS_PORT4_RX_CBCR 0x01868258
#define GCC_NSS_PORT4_TX_CBCR 0x0186825C
#define GCC_NSS_PORT5_RX_CBCR 0x01868260
#define GCC_NSS_PORT5_TX_CBCR 0x01868264
#define GCC_NSS_PPE_CBCR 0x01868190
#define GCC_NSS_PPE_CFG_CBCR 0x01868194
#define GCC_NSS_EDMA_CBCR 0x01868198
#define GCC_NSS_EDMA_CFG_CBCR 0x0186819C
#define GCC_NSS_PTP_REF_CBCR 0x0186816C
#define GCC_NSSNOC_PPE_CBCR 0x01868300
#define GCC_NSSNOC_PPE_CFG_CBCR 0x01868304
#define GCC_NSS_CRYPTO_CBCR 0x01868164
#define GCC_NSSNOC_SNOC_CBCR 0x01868188
#define GCC_SNOC_NSSNOC_CBCR 0x01826070
#define GCC_NSS_NOC_CBCR 0x01868168
#define GCC_NSSNOC_ATB_CBCR 0x0186818C
#define GCC_NSSNOC_QOSGEN_REF_CBCR 0x01868180
#define GCC_NSSNOC_TIMEOUT_REF_CBCR 0x01868184
#define GCC_NSS_CE_AXI_CBCR 0x01868170
#define GCC_NSS_CE_APB_CBCR 0x01868174
#define GCC_NSSNOC_CE_AXI_CBCR 0x01868308
#define GCC_NSSNOC_CE_APB_CBCR 0x0186830C
#define GCC_NSSNOC_UBI0_AHB_CBCR 0x01868270
#define GCC_NSS_CFG_CBCR 0x01868160
/*
* GCC-SDCC Registers
*/

4
drivers/net/ipq6018/ipq6018_uniphy.c
View file

@ -135,8 +135,6 @@ static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t channel)
{
uint32_t reg_value;
writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
@ -180,8 +178,6 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t channel)
static void ppe_uniphy_sgmii_plus_mode_set(uint32_t uniphy_index)
{
uint32_t reg_value;
writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +