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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-03 07:54:24 +01:00
Merge "drivers: net: ipq6018: Add support for AQ and SFP"
This commit is contained in:
commit
a54c74bd89
6 changed files with 36 additions and 59 deletions
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@ -101,7 +101,6 @@ CONFIG_CMD_NET=y
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CONFIG_QCA8075_PHY=y
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CONFIG_QCA8033_PHY=y
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CONFIG_QCA8081_PHY=y
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CONFIG_IPQ6018_QCA_AQUANTIA_PHY=y
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#
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# Misc commands
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@ -967,11 +967,13 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
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break;
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case FAL_SPEED_100:
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mac_speed = 0x1;
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if (i == aquantia_port && i == 4)
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if (i == aquantia_port) {
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speed_clock1 = 0x309;
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else
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speed_clock2 = 0x4;
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} else {
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speed_clock1 = 0x109;
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speed_clock2 = 0x0;
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speed_clock2 = 0x0;
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}
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printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
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priv->mac_unit, i, lstatus[status], speed,
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dp[duplex]);
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@ -985,12 +987,9 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
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break;
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case FAL_SPEED_1000:
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mac_speed = 0x2;
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if (i == aquantia_port) {
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if (i == 4)
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speed_clock1 = 0x304;
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else
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speed_clock1 = 0x104;
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} else
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if (i == aquantia_port)
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speed_clock1 = 0x304;
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else
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speed_clock1 = 0x101;
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speed_clock2 = 0x0;
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printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1005,6 +1004,11 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
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}
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break;
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case FAL_SPEED_2500:
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if (i == aquantia_port) {
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mac_speed = 0x4;
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speed_clock1 = 0x307;
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speed_clock2 = 0x0;
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}
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if (phy_node >= 0) {
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if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
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mac_speed = 0x2;
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@ -1014,23 +1018,7 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
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else if (i == 3)
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speed_clock1 = 0x101;
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speed_clock2 = 0x0;
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} else if (phy_info[i]->phy_type == AQ_PHY_TYPE) {
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mac_speed = 0x4;
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if (i == 4) {
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speed_clock1 = 0x301;
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speed_clock2 = 0x3;
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} else if (i == 3) {
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speed_clock1 = 0x107;
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speed_clock2 = 0x0;
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}
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}
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} else {
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mac_speed = 0x4;
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if (i == 4)
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speed_clock1 = 0x307;
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else
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speed_clock1 = 0x107;
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speed_clock2 = 0x0;
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}
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printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
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priv->mac_unit, i, lstatus[status], speed,
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@ -1038,10 +1026,7 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
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break;
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case FAL_SPEED_5000:
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mac_speed = 0x5;
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if (i == 4)
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speed_clock1 = 0x303;
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else
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speed_clock1 = 0x103;
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speed_clock1 = 0x303;
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speed_clock2 = 0x0;
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printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
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priv->mac_unit, i, lstatus[status], speed,
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@ -1049,10 +1034,7 @@ static int ipq6018_eth_init(struct eth_device *eth_dev, bd_t *this)
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break;
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case FAL_SPEED_10000:
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mac_speed = 0x3;
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if (i == 4)
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speed_clock1 = 0x301;
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else
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speed_clock1 = 0x101;
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speed_clock1 = 0x301;
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speed_clock2 = 0x0;
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printf ("eth%d PHY%d %s Speed :%d %s duplex\n",
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priv->mac_unit, i, lstatus[status], speed,
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@ -1685,6 +1667,9 @@ int ipq6018_edma_init(void *edma_board_cfg)
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if (node >= 0)
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port_8033 = fdtdec_get_uint(gd->fdt_blob, node, "8033_port", -1);
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if (node >= 0)
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aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1);
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phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo");
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if (phy_node >= 0)
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get_phy_address(phy_node);
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@ -205,8 +205,6 @@ int phy_status_get_from_ppe(int port_id)
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ipq6018_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, ®_field);
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if (port_id == (PORT5 - PPE_UNIPHY_INSTANCE1))
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reg_field >>= PORT_PHY_STATUS_PORT5_1_OFFSET;
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else
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reg_field >>= PORT_PHY_STATUS_PORT6_OFFSET;
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return ((reg_field >> 7) & 0x1) ? 0 : 1;
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}
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@ -324,14 +322,8 @@ void ipq6018_10g_r_speed_set(int port, int status)
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{
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uint32_t uniphy_index;
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/* Setting the speed only for PORT5 and PORT6 */
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if (port == (PORT4 - PPE_UNIPHY_INSTANCE0))
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uniphy_index = PPE_UNIPHY_INSTANCE0;
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else if (port == (PORT5 - PPE_UNIPHY_INSTANCE0))
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uniphy_index = PPE_UNIPHY_INSTANCE1;
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else
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return;
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/* Setting the speed only for PORT5 */
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uniphy_index = PPE_UNIPHY_INSTANCE1;
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ppe_xgmac_10g_r_speed_set(uniphy_index - 1);
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ppe_port_bridge_txmac_set(port + 1, status);
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ppe_port_txmac_status_set(uniphy_index - 1);
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@ -344,14 +336,8 @@ void ipq6018_uxsgmii_speed_set(int port, int speed, int duplex,
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{
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uint32_t uniphy_index;
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/* Setting the speed only for PORT5 and PORT6 */
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if (port == (PORT4 - PPE_UNIPHY_INSTANCE0))
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uniphy_index = PPE_UNIPHY_INSTANCE0;
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else if (port == (PORT5 - PPE_UNIPHY_INSTANCE0))
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uniphy_index = PPE_UNIPHY_INSTANCE1;
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else
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return;
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/* Setting the speed only for PORT5 */
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uniphy_index = PPE_UNIPHY_INSTANCE1;
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ppe_uniphy_usxgmii_autoneg_completed(uniphy_index);
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ppe_uniphy_usxgmii_speed_set(uniphy_index, speed);
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ppe_xgmac_speed_set(uniphy_index - 1, speed);
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@ -1148,11 +1134,16 @@ static void ppe_port_mux_set(int port_id, int port_type, int mode)
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}
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break;
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case 5:
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if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4)
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if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4) {
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port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
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else if (mode == PORT_WRAPPER_PSGMII)
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port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
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port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_GMAC;
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port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_GMAC;
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} else if (mode == PORT_WRAPPER_PSGMII) {
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port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
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port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_GMAC;
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} else if (mode == PORT_WRAPPER_USXGMII || mode == PORT_WRAPPER_10GBASE_R) {
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port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
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port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_XGMAC;
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}
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break;
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default:
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break;
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@ -123,8 +123,7 @@ union ipo_action_u {
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#define CPPE_DETECTION_PHY_FAILURE 0xFFFF
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#define PORT_PHY_STATUS_ADDRESS 0x44
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#define PORT_PHY_STATUS_PORT5_1_OFFSET 8
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#define PORT_PHY_STATUS_PORT6_OFFSET 16
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#define PORT_PHY_STATUS_PORT5_1_OFFSET 16
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#define IPQ6018_PPE_IPE_L3_BASE_ADDR 0x200000
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#define IPQ6018_PPE_L3_VP_PORT_TBL_ADDR (IPQ6018_PPE_IPE_L3_BASE_ADDR + 0x1000)
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@ -305,6 +305,7 @@ extern loff_t board_env_size;
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#define CONFIG_IPQ6018_TZ_WONCE_4_ADDR 0x193d010
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#define CONFIG_IPQ6018_EDMA 1
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#define CONFIG_IPQ6018_QCA_AQUANTIA_PHY 1
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#define CONFIG_IPQ6018_BRIDGED_MODE 1
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#define CONFIG_NET_RETRY_COUNT 5
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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@ -16,11 +16,13 @@
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/* ESS Switch Mac Modes */
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#define PORT_WRAPPER_PSGMII 0x0
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#define PORT_WRAPPER_USXGMII 0x2
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#define PORT_WRAPPER_SGMII_PLUS 0x6
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#define PORT_WRAPPER_10GBASE_R 0x7
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#define UNUSED 0xFF
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/* ETH PHY Types */
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#define MALIBU_PHY_TYPE 0x1
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#define QCA8081_PHY_TYPE 0x2
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#define AQ_PHY_TYPE 0x3
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#endif
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