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drivers: net: ipq: Fix 100M linking up as 10M issue

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Change-Id: I0910d3ee001c1daa2a7b70b5d5ffba8950e810a9
Signed-off-by: speriaka <speriaka@codeaurora.org>
This commit is contained in:
speriaka 2019-07-22 16:52:12 +05:30
parent 92bf8f1811
commit 07d7071ed1
2 changed files with 35 additions and 1 deletions
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22
drivers/net/ipq_common/ipq_qca8081.c
View file

@ -21,12 +21,19 @@
extern int ipq_mdio_read(int mii_id,
int regnum, ushort *data);
extern int ipq_mdio_write(int mii_id,
int regnum, u16 data);
u16 qca8081_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id)
{
return ipq_mdio_read(phy_id, reg_id, NULL);
}
u16 qca8081_phy_reg_write(u32 dev_id, u32 phy_id, u32 reg_id, u16 value)
{
return ipq_mdio_write(phy_id, reg_id, value);
}
u8 qca8081_phy_get_link_status(u32 dev_id, u32 phy_id)
{
u16 phy_data;
@ -86,6 +93,7 @@ int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id)
{
u16 phy_data;
struct phy_ops *qca8081_ops;
qca8081_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops));
if (!qca8081_ops)
return -ENOMEM;
@ -99,5 +107,17 @@ int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id)
phy_data = qca8081_phy_reg_read(0x0, phy_id, QCA8081_PHY_ID2);
printf ("PHY ID2: 0x%x\n", phy_data);
return 0;
/*enable vga when init napa to fix 8023az issue*/
phy_data = qca8081_phy_reg_read(0x0, phy_id, QCA808X_8023AZ_ENABLE_VGA);
phy_data &= (~QCA808X_PHY_8023AZ_AFE_CTRL_MASK);
phy_data |= QCA808X_PHY_8023AZ_AFE_EN;
phy_data = qca8081_phy_reg_write(0x0, phy_id, QCA808X_8023AZ_ENABLE_VGA, phy_data);
if (phy_data != 0)
return phy_data;
/*special configuration for AZ under 1G speed mode*/
phy_data = QCA808X_PHY_MMD3_AZ_TRAINING_VAL;
phy_data = qca8081_phy_reg_write(0x0, phy_id, QCA808X_AZ_CONFIG_UNDER_1G_SPEED,
phy_data);
return phy_data;
}

14
drivers/net/ipq_common/ipq_qca8081.h
View file

@ -45,4 +45,18 @@
#define QCA8081_STATUS_SPEED_100MBS 0x80
#define QCA8081_STATUS_SPEED_10MBS 0x0000
#define QCA808X_PHY_MMD3_AZ_TRAINING_VAL 0x1c32
#define QCA808X_PHY_MMD3_NUM 3
#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
#define QCA808X_PHY_8023AZ_AFE_CTRL_MASK 0x01f0
#define QCA808X_PHY_8023AZ_AFE_EN 0x0090
#define QCA808X_MII_ADDR_C45 (1<<30)
#define QCA808X_REG_C45_ADDRESS(dev_type, reg_num) (QCA808X_MII_ADDR_C45 | \
((dev_type & 0x1f) << 16) | (reg_num & 0xffff))
#define QCA808X_8023AZ_ENABLE_VGA QCA808X_REG_C45_ADDRESS(QCA808X_PHY_MMD3_NUM, \
QCA808X_PHY_MMD3_ADDR_CLD_CTRL7)
#define QCA808X_AZ_CONFIG_UNDER_1G_SPEED QCA808X_REG_C45_ADDRESS(QCA808X_PHY_MMD3_NUM, \
QCA808X_PHY_MMD3_AZ_TRAINING_CTRL)
#endif /* _QCA8081_PHY_H_ */