mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-09 10:47:41 +01:00
Merge "ipq5018: Enable support for serial nand in qpic"
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5d3735cfac
7 changed files with 1069 additions and 40 deletions
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@ -28,6 +28,11 @@
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compatible = "qcom,sdhci-msm";
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};
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nand: nand-controller@79B0000 {
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status = "ok";
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nand_gpio {};
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};
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timer {
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gpt_freq_hz = <240000>;
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};
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@ -62,4 +62,55 @@
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spi_gpio {};
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};
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nand: nand-controller@79B0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,qpic-nand-v2.1.1";
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reg = <0x79B0000 0x10000>;
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nand_gpio {
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qspi_data0 {
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gpio = <7>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_DISABLE>;
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};
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qspi_data1 {
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gpio = <6>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_DISABLE>;
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};
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qspi_data2 {
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gpio = <5>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_DISABLE>;
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};
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qspi_data3 {
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gpio = <4>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_DISABLE>;
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};
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qspi_cs_n {
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gpio = <8>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_DISABLE>;
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};
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qspi_clk {
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gpio = <9>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_DISABLE>;
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};
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};
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};
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};
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@ -94,11 +94,200 @@
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#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
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#define NAND_HW_INFO NAND_REG(0x00FC)
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#define NAND_FLASH_BUFFER NAND_REG(0x0100)
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#define NAND_FLASH_FEATURES NAND_REG(0x0F64)
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#define QPIC_NAND_CTRL NAND_REG(0x0F00)
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#define QPIC_NAND_DEBUG NAND_REG(0x0F0C)
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/* Additional Register set for Serial NAND */
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#define NAND_AUTO_STATUS_EN NAND_REG(0x002C)
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#define NAND_VERSION NAND_REG(0x4F08)
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#define SPI_NAND_DEV_CMD0 NAND_REG(0x70A0)
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#define SPI_NAND_DEV_CMD1 NAND_REG(0x70A4)
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#define SPI_NAND_DEV_CMD2 NAND_REG(0x70A8)
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#define SPI_NAND_DEV_CMD3 NAND_REG(0x70D0)
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#define NAND_FLASH_DEV_CMD_VLD NAND_REG(0x70AC)
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#define SPI_NAND_DEV_CMD7 NAND_REG(0x70B0)
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#define SPI_NAND_DEV_CMD8 NAND_REG(0x70B4)
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#define SPI_NAND_DEV_CMD9 NAND_REG(0x70B8)
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#define NAND_FLASH_SPI_CFG NAND_REG(0x70C0)
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#define NAND_SPI_NUM_ADDR_CYCLES NAND_REG(0x70C4)
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#define NAND_SPI_BUSY_CHECK_WAIT_CNT NAND_REG(0x70C8)
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/* Register mask & shift value used in SPI transfer mode */
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#define SPI_TRANSFER_MODE_1X 0x1
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#define SPI_TRANSFER_MODE_4X 0x3
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/* These value as per HPG , these value as per 2K device*/
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#define SPI_NAND_DEVn_CFG0 0x1A5408D0
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#define SPI_NAND_DEVn_CFG1 0x08287440
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#define SPI_NAND_DEVn_CFG1_RESET 0x087476B1
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/* value for below register according to HPG : 0x42040702 for reset
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* and 0x42040700 for reset disable
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*/
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#define SPI_NAND_DEVn_ECC_CFG 0x42040702
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#define SPI_NAND_DEVn_ECC_CFG_RST_DIS 0x42040700
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#define FLASH_DEV_CMD_VLD 0x0000000D
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/* These Value as per HPG */
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#define NAND_FLASH_DEV_CMD0_VAL 0x1080D8D8
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#define NAND_FLASH_DEV_CMD1_VAL 0xF00F3000
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#define NAND_FLASH_DEV_CMD2_VAL 0xF0FF709F
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#define NAND_FLASH_DEV_CMD3_VAL 0x3F310015
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/* For Micron NAND_FLASH_DEV_CMD3_VAL value should
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* be 0x3F300015
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*/
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#define NAND_FLASH_DEV_CMD7_VAL 0x04061F0F
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#define NAND_FLASH_DEV_CMD7_WE 0x60000
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#define NAND_FLASH_DEV_CMD7_WD 0x40000000
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#define NAND_FLASH_DEV_CMD7_SET_FTR 0x1F00
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#define NAND_FLASH_DEV_CMD7_GET_FTR 0x0F
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#define SPI_BUSY_CHECK_WAIT_CNT 0x00000010
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#define SPI_CFG_VAL 0x1924C00D
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#define SPI_LOAD_CLK_CNTR_INIT_EN (1 << 28)
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#define SPI_NUM_ADDR_CYCLES 0x000DA4DB
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#define NAND_FLASH_SET_FEATURE_MASK 0xB800000E
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#define NAND_FLASH_GET_FEATURE_MASK 0x3800000E
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#define QPIC_HARDWARE_VERSION_2_0 0x20000000
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#define NAND_FLASH_STATUS_MASK 0xC
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#define QPIC_SERIAL_ERROR 517
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#define QPIC_SPI_SET_FEATURE (1 << 31)
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#define QPIC_SPI_GET_FEATURE ~(1 << 31)
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#define QPIC_SPI_WP_SET (1 << 28)
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#define QPIC_SPI_HOLD_SET (1 << 27)
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#define QPIC_SPI_TRANSFER_MODE_X1 (1 << 29)
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#define QPIC_SPI_TRANSFER_MODE_X4 (3 << 29)
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#define QPIC_SPI_BOOST_MODE (1 << 11)
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#define QPIC_SPI_NAND_CTRL_VAL 0x341
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#define QPIC_SPI_NAND_AUTO_STATUS_VAL 0x003F003F
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#define QPIC_NAND_FLASH_CMD_WE_VAL 0XB800000F
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#define QPIC_NAND_FLASH_CMD_WD_VAL 0x3800000F
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#define WR_EN 0x1
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#define WR_DIS 0x0
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/* According to GigaDevice data sheet Block Protection Register is:
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* ____________________________________________
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* | | | | | | | | |
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* |BRWD |RSVD| BP2| BP1| BP0| INV | CMP |RSVD |
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* | | | | | | | | |
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* |______|____|____|____|____|_____|_____|_____|
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*
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* NOTE: RSVD = Reserved.
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*
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* After power-up the device is in "locked" state i.e feature bits
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* BP0, BP1, BP2 are set to 1. ENV, CMP, BRWD are set to 0.
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* When BRWD is set to 1 and WP# is LOW i.e 0, none of the writable
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* protection feature bits can be set.
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* When an ERASE command is issued to a locked block, the erase failure,
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* 04H, is returned.
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*
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* With CMP = X, INV = X, BP2 = 0, BP1 = 0, BP0 = 0 : There will be no
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* block protection functionality.
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*
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* When WP# is not LOW, user can issue bellows commands to alter the
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* protection.
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*
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* Issue SET FEATURES register write (1FH)
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* Issue the feature bit address (A0h)
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*/
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#define FLASH_SPI_NAND_BLK_PROCT_ADDR 0xA0
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#define FLASH_SPI_NAND_BLK_PROCT_DISABLE 0x00
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#define FLASH_SPI_NAND_BLK_PROCT_ENABLE 0x78
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/* According to GigaDevice data sheet Feature Register is:
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* _________________________________________________
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* | | | | | | | | |
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* |OTP-PRT|OTP_EN| RSVD|ECC-EN|RSVD|RSVD |RSVD |QE |
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* | | | | | | | | |
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* |_______|______|_____|______|____|_____|_____|____|
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*
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*
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* NOTE : When a feature is set, it remains active until the
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* device is power cycled or the feature is written to.once
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* the device is set, it remains set, even if a RESET (FFH)
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* command is issued.
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*
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* OTP-PRT = X , OTP_EN = 0 : Normal Operation
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* OTP-PRT = 0, OTP_EN = 1 : Access OTP region, read and program data.
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*
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* ECC-EN : ECC is enabled after device power up, so the default
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* READ and PROGRAM commands operate with internal ECC in the “active”
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* state. To enable/disable ECC, perform the following command sequence:
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*
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* 1) Issue the SET FEATURES command (1FH).
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* 2) Set the feature bit ECC_EN as you want:
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* a) To enable ECC, Set ECC_EN to 1.
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* b) To disable ECC, Clear ECC_EN to 0.
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*
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* NOTE: For this device GD5F1GQ4xExxG
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* --> Internal ECC Off (ECC_EN=0):
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* 2048-Byte+128-Byte Full Access.
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*
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* --> Internal ECC On (ECC_EN=1, default):
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* Program: 2048-Byte+64-Byte.
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* Read: 2048-Byte+128-Byte.
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*
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* QE : If QE is enabled, the quad IO operations can be executed.
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*
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*/
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#define FLASH_SPI_NAND_FR_ADDR 0xB0
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#define FLASH_SPI_NAND_FR_ECC_ENABLE (1 << 4)
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#define FLASH_SPI_NAND_FR_QUAD_ENABLE 0x1
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/* According to GigaDevice data sheet Status Register(0xC0) is:
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* _________________________________________________
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* | | | | | | | | |
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* |RSVD |RSVD |ECCS1|ECCS0|P-FAIL|E-FAIL|WEL |OIP |
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* | | | | | | | | |
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* |______|______|_____|_____|_____ |______|____|____|
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*
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*
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* NOTE: RSVD = Reserved.
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*
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* P-FAIL : This bit indicates that a program failure has occurred
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* (P_FAIL set to 1). It will also be set if the user attempts to
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* program an invalid address or a protected region, including
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* the OTP area.
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*
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* E-FAIL : This bit indicates that an erase failure has occurred
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* (E_FAIL set to 1). It will also be set if the user attempts to
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* erase a locked region.
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*
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* WEL : This bit indicates the current status of the write enable
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* latch (WEL) and must be set (WEL = 1), prior to issuing a
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* PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the
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* WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing
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* the WRITE DISABLE command.
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*
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* OIP : This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ,
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* BLOCK ERASE, or RESET command is executing, indicating the device
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* is busy. When the bit is 0, the interface is in the ready state.
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*
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* ECC Status : ECCS and ECCSE are set to 00b either following a RESET,
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* or at the beginning of the READ.ECCS and ECCSE are invalid if internal
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* ECC is disabled (via a SET FEATURES command to reset ECC_EN to 0).
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*
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* NOTE: After power-on RESET, ECC status is set to reflect the contents
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* of block 0, page 0.
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*/
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#define FLASH_SPI_NAND_SR_ADDR 0xC0
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#define FLASH_SPI_NAND_SR_DATA 0x00
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/* According to GigaDevice data sheet Feature Register(0xD0) is:
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* _________________________________________________
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* | | | | | | | | |
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* |RSVD |DS-S1|DS-S0|RSVD |RSVD |RSVD |RSVD |RSVD|
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* | | | | | | | | |
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* |______|_____|_____|_____|______|______|_____|____|
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*
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* DS-S1 = 0 , DS-S0 = 0 : Drive strength is 50%
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* DS-S1 = 0 , DS-S0 = 1 : Drive strength is 25%
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* DS-S1 = 1 , DS-S0 = 0 : Drive strength is 75%
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* DS-S1 = 1 , DS-S0 = 1 : Drive strength is 100%
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*
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* 00 is the default data byte value for Output Driver Register after power-up
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*/
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#define FLASH_SPI_NAND_FR_DS_ADDR 0xD0
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#define FLASH_SPI_NAND_FR_DS_DATA 0x00
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/* NANDc registers used during BAM transfer */
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#define NAND_READ_LOCATION_n(n) (NAND_REG(0xF20) + 4 * (n))
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#define NAND_READ_LOCATION_LAST_CW_n(n) (NAND_REG(0xF40) + 4 * (n))
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#define NAND_RD_LOC_LAST_BIT(x) ((x) << 31)
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#define NAND_RD_LOC_SIZE(x) ((x) << 16)
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#define NAND_RD_LOC_OFFSET(x) ((x) << 0)
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@ -151,6 +340,23 @@
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#define NAND_CMD_BLOCK_ERASE 0x3A
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#define NAND_CMD_FETCH_ID 0x0B
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#define NAND_CMD_RESET_DEVICE 0x0D
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#define NAND_CMD_SET_FEATURE 0x1F
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#define NAND_CMD_GET_FEATURE 0x0F
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#define NAND_CMD_ACC_FEATURE 0x0E
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/* Serial NAND Device command */
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#define SERIAL_NAND_CMD_READ_FROM_CACHE_X4 0x6B
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#define SERIAL_NAND_CMD_READ_FROM_CACHE_DUAL_IO 0xBB
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#define SERIAL_NAND_CMD_READ_FROM_CACHE_QUAD_IO 0xEB
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#define SERIAL_NAND_CMD_READ_ID 0x9F
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#define SERIAL_NAND_CMD_PROGRAM_LOAD 0x02
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#define SERIAL_NAND_CMD_PROGRAM_LOAD_X4 0x32
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#define SERIAL_NAND_CMD_PROGRAM_EXECUTE 0x10
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#define SERIAL_NAND_CMD_PROGRAM_LOAD_RND_DATA 0x84
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#define SERIAL_NAND_CMD_PROGRAM_LOAD_RND_DATA_X4 0xC4 /* Or 0x34 */
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#define SERIAL_NAND_CMD_PROGRAM_LOAD_QUAD_IO 0x72
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#define SERIAL_NAND_CMD_BLOCK_ERASE 0xD8
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#define SERIAL_NAND_CMD_RESET 0xFF
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/* NAND Status errors */
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#define NAND_FLASH_MPU_ERR (1 << 8)
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#define NAND_FLASH_TIMEOUT_ERR (1 << 6)
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@ -170,6 +376,7 @@
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#define DATA_CONSUMER_PIPE_INDEX 0
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#define DATA_PRODUCER_PIPE_INDEX 1
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#define CMD_PIPE_INDEX 2
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#define BAM_STATUS_PIPE_INDEX 3
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/* Define BAM pipe lock groups for NANDc*/
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#define P_LOCK_GROUP_0 0
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@ -238,11 +445,13 @@
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#define DATA_CONSUMER_PIPE 0
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#define DATA_PRODUCER_PIPE 1
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#define CMD_PIPE 2
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#define NAND_BAM_STATUS_PIPE 3
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/* NANDc BAM pipe groups */
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#define DATA_PRODUCER_PIPE_GRP 0
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#define DATA_CONSUMER_PIPE_GRP 0
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#define CMD_PIPE_GRP 1
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#define NAND_BAM_STATUS_PIPE_GRP 2
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/* NANDc EE */
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#define QPIC_NAND_EE 0
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|
@ -252,6 +461,7 @@
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/* Register: NAND_CTRL */
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#define BAM_MODE_EN 0x1
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#define NANDC_READ_DELAY_COUNTER_VAL 0x340
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/* Register: NAND_DEBUG */
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#define BAM_MODE_BIT_RESET (1 << 31)
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|
@ -277,6 +487,7 @@
|
|||
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#define QPIC_BAM_DATA_FIFO_SIZE 64
|
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#define QPIC_BAM_CMD_FIFO_SIZE 64
|
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#define QPIC_BAM_STATUS_FIFO_SIZE 64
|
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|
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#define QPIC_MAX_ONFI_MODES 4
|
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#define QPIC_NUM_XFER_STEPS 7
|
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|
|
@ -284,7 +495,7 @@
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enum qpic_verion{
|
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QCA_QPIC_V1_4_20,
|
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QCA_QPIC_V1_5_20,
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|
||||
QCA_QPIC_V2_1_1,
|
||||
};
|
||||
|
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|
|
@ -311,6 +522,28 @@ enum nand_cfg_value
|
|||
NAND_CFG,
|
||||
};
|
||||
|
||||
/* Structure for Serial nand parameter */
|
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struct qpic_serial_nand_params {
|
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u8 id[4];
|
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u16 page_size;
|
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u16 pgs_per_blk;
|
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u32 spare_size;
|
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u32 erase_blk_size;
|
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u16 no_of_blocks;
|
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u32 density;
|
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u32 otp_region;
|
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u8 no_of_addr_cycle;
|
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u8 no_of_dies;
|
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u8 num_bits_ecc_correctability;
|
||||
u8 timing_mode_support;
|
||||
bool quad_mode;
|
||||
bool check_quad_config;
|
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int prev_die_id;
|
||||
u8 protec_bpx;
|
||||
u64 pages_per_die;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
struct onfi_param_page
|
||||
{
|
||||
uint32_t signature;
|
||||
|
|
@ -396,9 +629,15 @@ struct qpic_nand_bam_pipes
|
|||
unsigned read_pipe;
|
||||
unsigned write_pipe;
|
||||
unsigned cmd_pipe;
|
||||
#if defined(QPIC_SERIAL) && defined(MULTI_PAGE_READ)
|
||||
unsigned status_pipe;
|
||||
#endif
|
||||
uint8_t read_pipe_grp;
|
||||
uint8_t write_pipe_grp;
|
||||
uint8_t cmd_pipe_grp;
|
||||
#if defined(QPIC_SERIAL) && defined(MULTI_PAGE_READ)
|
||||
uint8_t status_pipe_grp;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Structure to define the initial nand config */
|
||||
|
|
@ -442,6 +681,10 @@ struct qpic_nand_dev {
|
|||
uint32_t cfg0_raw;
|
||||
uint32_t cfg1_raw;
|
||||
uint32_t ecc_bch_cfg;
|
||||
#ifdef CONFIG_QPIC_SERIAL
|
||||
bool quad_mode;
|
||||
bool check_quad_config;
|
||||
#endif
|
||||
unsigned oob_per_page;
|
||||
unsigned char *buffers;
|
||||
unsigned char *pad_dat;
|
||||
|
|
|
|||
|
|
@ -290,8 +290,17 @@ void reset_crashdump(void)
|
|||
return;
|
||||
}
|
||||
|
||||
void qpic_clk_enbale(void)
|
||||
{
|
||||
writel(QPIC_CBCR_VAL, GCC_QPIC_CBCR_ADDR);
|
||||
writel(0x1, GCC_QPIC_AHB_CBCR_ADDR);
|
||||
writel(0x1, GCC_QPIC_IO_MACRO_CBCR);
|
||||
}
|
||||
|
||||
void board_nand_init(void)
|
||||
{
|
||||
qpic_nand_init();
|
||||
|
||||
#ifdef CONFIG_QCA_SPI
|
||||
int gpio_node;
|
||||
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
|
||||
|
|
|
|||
|
|
@ -35,6 +35,15 @@
|
|||
#define GCC_SDCC1_AHB_CBCR 0x0184201C
|
||||
#define GCC_SDCC1_MISC 0x01842020
|
||||
|
||||
/*
|
||||
* GCC-QPIC Registers
|
||||
*/
|
||||
#define GCC_QPIC_IO_MACRO_CBCR 0x0185701C
|
||||
#define GCC_QPIC_CBCR_ADDR 0x01857020
|
||||
#define GCC_QPIC_AHB_CBCR_ADDR 0x01857024
|
||||
#define GCC_QPIC_SLEEP_CBCR 0x01857028
|
||||
#define QPIC_CBCR_VAL 0x80004FF1
|
||||
|
||||
/* UART 1 */
|
||||
#define GCC_BLSP1_UART1_BCR 0x01802038
|
||||
#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203C
|
||||
|
|
@ -118,6 +127,7 @@ struct smem_ram_ptable {
|
|||
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
|
||||
void reset_crashdump(void);
|
||||
void reset_board(void);
|
||||
void qpic_clk_enbale(void);
|
||||
|
||||
typedef enum {
|
||||
SMEM_SPINLOCK_ARRAY = 7,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -130,6 +130,10 @@ extern loff_t board_env_size;
|
|||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* QSPI Flash configs
|
||||
*/
|
||||
#define CONFIG_QPIC_SERIAL
|
||||
|
||||
/*
|
||||
* SPI Flash Configs
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue