This change set SGMII mode and force mode based on
dts entries.
Change-Id: Ideaa1bb77fe8fb37a7e6b907a987f6dcac54917f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes enable both PHY and switch configure
simultaneously and also switch can be configure
to any port.
And also these changes enable dual MDIO bus support.
Change-Id: Ib86c8a15abb9a7a35aa86d87cef78ad917dd1a00
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Add skip_pci_mask environment variable to skip pci enumeration
based on the bitmask. Also, removing the pci3 dts entry from
the RDP437 & RDP461 to skip pci3 enumeration.
Example - setenv skip_pci_mask 0xc
The above command will skip pci enumeration of bus 2 & 3.
Change-Id: Iff50acca07ffc026bed84a0d2372e6de0a3ba3a9
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Added JTAG ID, Serial number and Part type read.
Change-Id: Ia03724116230a157fc33406a97c641e3b5750d6a
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
It has the capacity of 1Gbit, i.e., 128MB, so
the number of blocks has been updated to 1024.
1Gbits = 128MB = 2048(page) * 64 (pages per block) * 1024 (blocks)
Change-Id: I552776e4e151d16782db915c3ebae874c5c02696
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
Added new config called CONFIG_QCA8084_BYPASS_MODE and moved
all the qca8084 by-pass mode related code under it.
Change-Id: I4157960989cd67576803d494594869265fc81745
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Added QCA8084 by-pass mode support on MI01.1 RDP
Change-Id: I1a14729cac5463675f9cb0d15df3da76746aa81e
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
These changes update config as like below.
1.Config 100M, 1G as GMAC, 2.5G as XGMAC
2.Config MHT as XGMAC.
Change-Id: I0566f3a3d364931e8c8173c3604160f24c2439be
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Added QCN92xx's SoC global reset and MHI reset in the fuse blow path.
So, the fuse blow can be retried after any failed attempts.
Added ANTI ROLLBACK fuse read.
Change-Id: Ibf255390ffc2086fcbfa9041dc0bcb612f8d9a4e
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
This changes includes update the Speed clock,
common clock update and dts nodes.
Change-Id: I673e8ccf191048fef966a8f6cd84858e1a3b824f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Only one SFP port can be enabled at time with
either SGMII or SGMII PLUS mode.
Mode shall be specified from dts for 1G or 2.5G
support respectively. Add below change to enable
SFP as this change is not mainlined.
gmac_cfg {
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
- phy_address = <0x1c>;
- napa_gpio = <39>;
/*
* 6 - SGMII_PLUS (2.5G),
* 8 - SGMII_FIBER (1G)
*/
+ switch_mac_mode = <8>;
+ sfp_tx_gpio = <27>;
+ sfp_rx_gpio = <29>;
};
};
Change-Id: I507be2b84b1f932802659abffa3288e304e0d411
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
"list_qcn9224_fuse" command will print the OEM ID, Secure boot enable
and OEM PK hash details of QCN9224 from all attached PCIe slots.
Change-Id: I87be2f58bcef6898a00f4e179c87f2dcb93a2604
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
This change will add support for giga device GD5F1GM7REYIG
spi nand support.
Change-Id: Ie32cb6824bd0fbcf04449fa070005b7fa323c025
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This change adds usxgmii support in UNIPHY0.
Earlier it was supported up to PSGMII with 4 ports.
With these changes,
UNIPHY0 supports either of the 2 modes mentioned below.
1. PSGMII with 4 ports
2. USXGMII with 1 port
Change-Id: Ic4ca62e3ef74d275cda92d86b459d204ee4325ed
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change adds a new command to support the qcn9224 fusing.
Fuser blower binary should be transfered via tftp to Host and
using fuse_qcn9224 command, binary can be transfered to qcn9224.
qcn9224 will take care of the fusing.
sample command:
tftpboot fuse_blower.bin
fuse_qcn9224 0
Change-Id: Ie8cd73a2d49799100bd1f717cdc4b8dad070f9bd
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
During long run tests on image download in u-boot,
EDMA crash was observed as the SKB buffer address
returned by the RX descriptor was corrupted and was
pointing to an invalid address:
clean_rx: p: 14 c: 0 skb: 61763b10
WARN: src_info_type:0x0. Drop skb:61763b10
The reason for corruption seems to be the RX buffer allocation that was
happening twice before initiating the EDMA for the next transaction.
This change removes the additional allocation of the Rx buffer which is
not needed.
Change-Id: I4a5b404527469ff3b981749aa4e05080f55807cd
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
During long run tests on image download in u-boot,
EDMA crash was observed as the SKB buffer address
returned by the RX descriptor was corrupted and was
pointing to an invalid address:
clean_rx: p: 14 c: 0 skb: 61763b10
WARN: src_info_type:0x0. Drop skb:61763b10
The reason for corruption seems to be the RX buffer allocation that was
happening twice before initiating the EDMA for the next transaction.
This change removes the additional allocation of the Rx buffer which is
not needed.
Change-Id: I919024df8131fe87640ecc0d481b61012742efbf
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
This patch adds a new command support to detect the qcn9224 version.
Based on "detect_qcn9224" command, change configures the BAR0 on EP,
does the window mapping and reads the HW version register. Version
value will be populated in "qcn9224_version" env. Version env will
be zero if there is no qcn9224 attach.
Change-Id: I4f4477590b439f31b46cb0b895dc0d9f8279a064
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
