mirror/u-boot-2016
1
0
Fork 0
mirror of https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git synced 2025-12-10 07:44:53 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

drivers: net: ipq9574: update uniphy SGMII config

Browse source 
This change set SGMII mode and force mode based on
dts entries.

Change-Id: Ideaa1bb77fe8fb37a7e6b907a987f6dcac54917f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy 2023-02-27 21:10:41 +05:30
parent 72b0604461
commit bd47dbed37
3 changed files with 23 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/dts/ipq9574-al02-c10.dts
View file

@ -23,6 +23,7 @@
* QCA8084 PHY
*/
qca8084_swt_port = <0>;
uniphy_force_mode = <0>;
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
qca8084_swt_info {

5
drivers/net/ipq9574/ipq9574_ppe.c
View file

@ -32,6 +32,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define pr_info(fmt, args...) printf(fmt, ##args);
int uniphy_force_mode;
extern int is_uniphy_enabled(int uniphy_index);
extern void uniphy_port5_clock_source_set(void);
@ -1012,6 +1014,9 @@ void ipq9574_ppe_interface_mode_init(void)
return;
}
uniphy_force_mode = fdtdec_get_uint(gd->fdt_blob, node,
"uniphy_force_mode", -1);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE2, mode2);

26
drivers/net/ipq9574/ipq9574_uniphy.c
View file

@ -27,6 +27,8 @@
#include <fdtdec.h>
#include "ipq_phy.h"
extern int uniphy_force_mode;
extern int is_uniphy_enabled(int uniphy_index);
DECLARE_GLOBAL_DATA_PTR;
@ -235,29 +237,35 @@ static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
mdelay(100);
}
void ppe_uniphy_set_forceMode(void)
void ppe_uniphy_set_forceMode(uint32_t uniphy_index)
{
uint32_t reg_value;
reg_value = readl(PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
reg_value |= UNIPHY_FORCE_SPEED_25M;
writel(reg_value, PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
}
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
{
if (uniphy_index == 0) {
writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET);
writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) +
UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET);
ppe_uniphy_set_forceMode();
if (uniphy_force_mode == uniphy_index)
ppe_uniphy_set_forceMode(uniphy_index);
if (mode == EPORT_WRAPPER_SGMII_PLUS) {
writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
(uniphy_index * PPE_UNIPHY_REG_INC) +
UNIPHY_MISC2_REG_OFFSET);
} else {
writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
(uniphy_index * PPE_UNIPHY_REG_INC) +
UNIPHY_MISC2_REG_OFFSET);
}
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +