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pci: ipq9574: Fix PCIe single lane PHY configuration

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Change-Id: Ie4f6f92a1cdb91b4cd97ec6ff1a80cef5780f162
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
This commit is contained in:
Praveenkumar I 2023-02-24 10:05:00 +05:30
parent 90c4bba23c
commit 4a2716fc06
1 changed files with 2 additions and 2 deletions
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4
drivers/pci/pci_ipq.c
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@ -670,7 +670,7 @@ static const struct phy_regs pcie_phy_v2_x2_init_seq_ipq[] = {
};
static const struct phy_regs pcie_phy_v2_init_seq_ipq[] = {
#if !defined(CONFIG_IPQ6018)
#if defined(CONFIG_IPQ807x)
{ PCS_COM_POWER_DOWN_CONTROL, 0x00000001},
{ PCIE_0_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x00000018},
{ PCIE_0_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x00000001},
@ -928,7 +928,7 @@ static const struct phy_regs pcie_phy_v2_init_seq_ipq[] = {
{ PCIE_0_PCS_COM_SW_RESET, 0x00000000},
{ PCIE_0_PCS_COM_START_CONTROL, 0x00000002},
{ PCIE_0_PCS_COM_START_CONTROL, 0x00000003},
#else
#elif defined(CONFIG_IPQ6018)
{ PCIE_0_PCS_COM_POWER_DOWN_CONTROL, 0x03 },
{ PCIE_0_QSERDES_PLL_SSC_PER1, 0x7D },
{ PCIE_0_QSERDES_PLL_SSC_PER2, 0x01 },