ipq5332: replace soc name from devsoc to ipq5332 in all file contents

Change-Id: Id5dd98e749bfd229e2c6e9d1944db397d2380cb1 Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
2025-12-10 07:44:53 +01:00 · 2022-09-27 17:12:56 +05:30 · 2022-09-27 17:12:56 +05:30 · 95e16ef259
commit 95e16ef259
parent b12ecdc358
44 changed files with 996 additions and 996 deletions
--- a/2
+++ b/2
@ -578,7 +578,7 @@ else
 ifdef CONFIG_ARCH_IPQ5018
 KBUILD_CFLAGS += $(call cc-option,-fstack-protector)
 else
-ifdef CONFIG_ARCH_DEVSOC
+ifdef CONFIG_ARCH_IPQ5332
 KBUILD_CFLAGS += $(call cc-option,-fstack-protector)
 else
 ifdef CONFIG_ARCH_IPQ6018
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@ -461,8 +461,8 @@ config ARCH_IPQ5018
 	select SYS_GENERIC_BOARD
 	select QCA_COMMON

-config ARCH_DEVSOC
-	bool "QCA, DEVSOC"
+config ARCH_IPQ5332
+	bool "QCA, IPQ5332"
 	select DM
 	select DM_SERIAL
 	select CPU_V7
@ -874,7 +874,7 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/imx31_phycore/Kconfig"
 source "board/ipq40xx/Kconfig"
 source "board/ipq5018/Kconfig"
-source "board/devsoc/Kconfig"
+source "board/ipq5332/Kconfig"
 source "board/ipq6018/Kconfig"
 source "board/ipq806x/Kconfig"
 source "board/ipq9574/Kconfig"
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@ -48,7 +48,7 @@ save_boot_params_ret:
 	msr	cpsr,r0

 #if defined (CONFIG_ARCH_IPQ807x) || defined (CONFIG_ARCH_IPQ6018) \
-	|| defined (CONFIG_ARCH_IPQ5018) || defined (CONFIG_ARCH_DEVSOC) \
+	|| defined (CONFIG_ARCH_IPQ5018) || defined (CONFIG_ARCH_IPQ5332) \
 	|| defined (CONFIG_ARCH_IPQ9574)
 /* Setup CP15 barrier */
 	mrc p15, 0, r0, c1, c0, 0 @Read SCTLR to r0
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@ -91,12 +91,12 @@ dtb-$(CONFIG_ARCH_IPQ5018) += ipq5018-db-mp02.1.dtb \
 				ipq5018-db-mp03.1.dtb
 endif

-dtb-$(CONFIG_ARCH_DEVSOC) += devsoc-emulation.dtb \
-				devsoc-01.1.dtb \
-				devsoc-01.2.dtb \
-				devsoc-01.4.dtb \
-				devsoc-01.6.dtb \
-				devsoc-01.7.dtb
+dtb-$(CONFIG_ARCH_IPQ5332) += ipq5332-emulation.dtb \
+				ipq5332-mi01.1.dtb \
+				ipq5332-mi01.2.dtb \
+				ipq5332-mi01.4.dtb \
+				ipq5332-mi01.6.dtb \
+				ipq5332-mi01.7.dtb

 dtb-$(CONFIG_ARCH_IPQ6018) += ipq6018-cp01-c1.dtb \
 			ipq6018-cp02-c1.dtb \
--- a/arch/arm/dts/ipq5332-emulation.dts
+++ b/arch/arm/dts/ipq5332-emulation.dts
@ -14,10 +14,10 @@
 */

 /dts-v1/;
-#include "devsoc-soc.dtsi"
+#include "ipq5332-soc.dtsi"
 / {
-	model ="QCA, DEVSOC-EMULATION";
-	compatible = "qca,devsoc", "qca,devsoc-emulation";
+	model ="QCA, IPQ5332-EMULATION";
+	compatible = "qca,ipq5332", "qca,ipq5332-emulation";
 	machid = <0xF060000>;
 	config_name = "config@emulation-fbc";

--- a/arch/arm/dts/ipq5332-mi01.1.dts
+++ b/arch/arm/dts/ipq5332-mi01.1.dts
@ -14,10 +14,10 @@
 */

 /dts-v1/;
-#include "devsoc-soc.dtsi"
+#include "ipq5332-soc.dtsi"
 / {
 	machid = <0x8060000>;
-	config_name = "config@01.1";
+	config_name = "config@mi01.1";

 	aliases {
 		console = "/serial@78AF000";
--- a/arch/arm/dts/ipq5332-mi01.2.dts
+++ b/arch/arm/dts/ipq5332-mi01.2.dts
@ -14,10 +14,10 @@
 */

 /dts-v1/;
-#include "devsoc-soc.dtsi"
+#include "ipq5332-soc.dtsi"
 / {
 	machid = <0x8060001>;
-	config_name = "config@01.2";
+	config_name = "config@mi01.2";

 	aliases {
 		console = "/serial@78AF000";
--- a/arch/arm/dts/ipq5332-mi01.4.dts
+++ b/arch/arm/dts/ipq5332-mi01.4.dts
@ -14,10 +14,10 @@
 */

 /dts-v1/;
-#include "devsoc-soc.dtsi"
+#include "ipq5332-soc.dtsi"
 / {
 	machid = <0x8060003>;
-	config_name = "config@01.4";
+	config_name = "config@mi01.4";

 	aliases {
 		console = "/serial@78AF000";
--- a/arch/arm/dts/ipq5332-mi01.6.dts
+++ b/arch/arm/dts/ipq5332-mi01.6.dts
@ -14,8 +14,8 @@
 */

 /dts-v1/;
-#include "devsoc-01.4.dts"
+#include "ipq5332-mi01.4.dts"
 / {
 	machid = <0x8060006>;
-	config_name = "config@01.6";
+	config_name = "config@mi01.6";
 };
--- a/arch/arm/dts/ipq5332-mi01.7.dts
+++ b/arch/arm/dts/ipq5332-mi01.7.dts
@ -14,8 +14,8 @@
 */

 /dts-v1/;
-#include "devsoc-01.1.dts"
+#include "ipq5332-mi01.1.dts"
 / {
 	machid = <0x8060007>;
-	config_name = "config@01.7";
+	config_name = "config@mi01.7";
 };
--- a/arch/arm/dts/ipq5332-soc.dtsi
+++ b/arch/arm/dts/ipq5332-soc.dtsi
@ -14,8 +14,8 @@
 */

 #include "skeleton.dtsi"
-#include <dt-bindings/qcom/gpio-devsoc.h>
-#include <dt-bindings/qcom/eth-devsoc.h>
+#include <dt-bindings/qcom/gpio-ipq5332.h>
+#include <dt-bindings/qcom/eth-ipq5332.h>

 / {
 	serial@78AF000 {
@ -59,7 +59,7 @@
 	};

 	pci0: pci@20000000 {
-		compatible = "qcom,devsoc-pcie";
+		compatible = "qcom,ipq5332-pcie";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x20000000 0xf1d
@ -78,7 +78,7 @@
 	};

 	pci1: pci@18000000 {
-		compatible = "qcom,devsoc-pcie";
+		compatible = "qcom,ipq5332-pcie";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x18000000 0xf1d
@ -97,7 +97,7 @@
 	};

 	pci2: pci@10000000 {
-		compatible = "qcom,devsoc-pcie";
+		compatible = "qcom,ipq5332-pcie";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x10000000 0xf1d
--- a/arch/arm/include/asm/arch-ipq5332/clk.h
+++ b/arch/arm/include/asm/arch-ipq5332/clk.h
@ -13,8 +13,8 @@
 * GNU General Public License for more details.
 */

-#ifndef _DEVSOC_CLK_H
-#define _DEVSOC_CLK_H
+#ifndef _IPQ5332_CLK_H
+#define _IPQ5332_CLK_H

 #include <asm/arch-qca-common/uart.h>

@ -321,4 +321,4 @@ enum uniphy_clk_type {

 void eth_clock_init(void);

-#endif /*DEVSOC_CLK_H*/
+#endif /*IPQ5332_CLK_H*/
--- a/arch/arm/include/asm/arch-ipq5332/edma_regs.h
+++ b/arch/arm/include/asm/arch-ipq5332/edma_regs.h
@ -21,236 +21,236 @@
 #ifndef __EDMA_REGS__
 #define __EDMA_REGS__

-#define DEVSOC_EDMA_CFG_BASE			0x3ab00000
+#define IPQ5332_EDMA_CFG_BASE			0x3ab00000

 /*
- * DEVSOC EDMA register offsets
+ * IPQ5332 EDMA register offsets
 */
-#define DEVSOC_EDMA_REG_MAS_CTRL		0x0
-#define DEVSOC_EDMA_REG_PORT_CTRL		0x4
-#define DEVSOC_EDMA_REG_RXDESC2FILL_MAP_0	0x14
-#define DEVSOC_EDMA_REG_RXDESC2FILL_MAP_1	0x18
-#define DEVSOC_EDMA_REG_DMAR_CTRL		0x48
-#define DEVSOC_EDMA_REG_MISC_INT_STAT		0x5c
-#define DEVSOC_EDMA_REG_MISC_INT_MASK		0x60
-#define DEVSOC_EDMA_REG_TXDESC2CMPL_MAP_0	0x8c
-#define DEVSOC_EDMA_REG_TXDESC2CMPL_MAP_1	0x90
-#define DEVSOC_EDMA_REG_TXDESC2CMPL_MAP_2	0x94
-#define DEVSOC_EDMA_REG_TXDESC2CMPL_MAP_3	0x98
-#define DEVSOC_EDMA_REG_MDIO_SLV_PASUE_MAP_0	0xA4
-#define DEVSOC_EDMA_REG_MDIO_SLV_PASUE_MAP_1	0xA8
+#define IPQ5332_EDMA_REG_MAS_CTRL		0x0
+#define IPQ5332_EDMA_REG_PORT_CTRL		0x4
+#define IPQ5332_EDMA_REG_RXDESC2FILL_MAP_0	0x14
+#define IPQ5332_EDMA_REG_RXDESC2FILL_MAP_1	0x18
+#define IPQ5332_EDMA_REG_DMAR_CTRL		0x48
+#define IPQ5332_EDMA_REG_MISC_INT_STAT		0x5c
+#define IPQ5332_EDMA_REG_MISC_INT_MASK		0x60
+#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_0	0x8c
+#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_1	0x90
+#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_2	0x94
+#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_3	0x98
+#define IPQ5332_EDMA_REG_MDIO_SLV_PASUE_MAP_0	0xA4
+#define IPQ5332_EDMA_REG_MDIO_SLV_PASUE_MAP_1	0xA8

-#define DEVSOC_EDMA_REG_TXDESC_BA(n)		(0x1000 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXDESC_PROD_IDX(n)	(0x1004 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXDESC_CONS_IDX(n)	(0x1008 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXDESC_RING_SIZE(n)	(0x100c + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXDESC_CTRL(n)		(0x1010 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXDESC_BA2(n)		(0x1014 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXDESC_BA(n)		(0x1000 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXDESC_PROD_IDX(n)	(0x1004 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXDESC_CONS_IDX(n)	(0x1008 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXDESC_RING_SIZE(n)	(0x100c + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXDESC_CTRL(n)		(0x1010 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXDESC_BA2(n)		(0x1014 + (0x1000 * n))

-#define DEVSOC_EDMA_REG_RXFILL_BA(n)		(0x29000 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXFILL_PROD_IDX(n)	(0x29004 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXFILL_CONS_IDX(n)	(0x29008 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXFILL_RING_SIZE(n)	(0x2900c + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXFILL_RING_EN(n)	(0x2901c + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXFILL_INT_STAT(n)	(0x31000 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXFILL_INT_MASK(n)	(0x31004 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXFILL_BA(n)		(0x29000 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXFILL_PROD_IDX(n)	(0x29004 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXFILL_CONS_IDX(n)	(0x29008 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXFILL_RING_SIZE(n)	(0x2900c + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXFILL_RING_EN(n)	(0x2901c + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXFILL_INT_STAT(n)	(0x31000 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXFILL_INT_MASK(n)	(0x31004 + (0x1000 * n))

-#define DEVSOC_EDMA_REG_RXDESC_BA(n)		(0x39000 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_PROD_IDX(n)	(0x39004 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_CONS_IDX(n)	(0x39008 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_RING_SIZE(n)	(0x3900c + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_FC_THRE(n)	(0x39010 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_CTRL(n)		(0x39018 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_BA2(n)		(0x39028 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_INT_STAT(n)	(0x59000 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RXDESC_INT_MASK(n)	(0x59004 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_RX_INT_CTRL(n)		(0x5900c + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_BA(n)		(0x39000 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_PROD_IDX(n)	(0x39004 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_CONS_IDX(n)	(0x39008 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_RING_SIZE(n)	(0x3900c + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_FC_THRE(n)	(0x39010 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_CTRL(n)		(0x39018 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_BA2(n)		(0x39028 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_INT_STAT(n)	(0x59000 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RXDESC_INT_MASK(n)	(0x59004 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_RX_INT_CTRL(n)		(0x5900c + (0x1000 * n))

-#define DEVSOC_EDMA_REG_TXCMPL_BA(n)		(0x79000 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXCMPL_PROD_IDX(n)	(0x79004 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXCMPL_CONS_IDX(n)	(0x79008 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXCMPL_RING_SIZE(n)	(0x7900c + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TXCMPL_CTRL(n)		(0x79014 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXCMPL_BA(n)		(0x79000 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXCMPL_PROD_IDX(n)	(0x79004 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXCMPL_CONS_IDX(n)	(0x79008 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXCMPL_RING_SIZE(n)	(0x7900c + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TXCMPL_CTRL(n)		(0x79014 + (0x1000 * n))

-#define DEVSOC_EDMA_REG_TX_INT_STAT(n)		(0x99000 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TX_INT_MASK(n)		(0x99004 + (0x1000 * n))
-#define DEVSOC_EDMA_REG_TX_INT_CTRL(n)		(0x9900c + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TX_INT_STAT(n)		(0x99000 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TX_INT_MASK(n)		(0x99004 + (0x1000 * n))
+#define IPQ5332_EDMA_REG_TX_INT_CTRL(n)		(0x9900c + (0x1000 * n))

 /*
 * EDMA QID2RID configuration
 */
-#define DEVSOC_EDMA_QID2RID_TABLE_MEM(q)	(0xb9000 + (0x4 * q))
+#define IPQ5332_EDMA_QID2RID_TABLE_MEM(q)	(0xb9000 + (0x4 * q))

-#define DEVSOC_EDMA_CPU_PORT_MC_QID_MIN	256
-#define DEVSOC_EDMA_CPU_PORT_MC_QID_MAX	271
-#define DEVSOC_EDMA_QID2RID_NUM_PER_REG	4
+#define IPQ5332_EDMA_CPU_PORT_MC_QID_MIN	256
+#define IPQ5332_EDMA_CPU_PORT_MC_QID_MAX	271
+#define IPQ5332_EDMA_QID2RID_NUM_PER_REG	4

 /*
 * EDMA_REG_DMAR_CTRL register
 */
-#define DEVSOC_EDMA_DMAR_REQ_PRI_MASK			0x7
-#define DEVSOC_EDMA_DMAR_REQ_PRI_SHIFT			0x0
-#define DEVSOC_EDMA_DMAR_BURST_LEN_MASK		0x1
-#define DEVSOC_EDMA_DMAR_BURST_LEN_SHIFT		3
-#define DEVSOC_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK	0x1f
-#define DEVSOC_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT	4
-#define DEVSOC_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK	0x7
-#define DEVSOC_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT	9
-#define DEVSOC_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK	0x7
-#define DEVSOC_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT	12
+#define IPQ5332_EDMA_DMAR_REQ_PRI_MASK			0x7
+#define IPQ5332_EDMA_DMAR_REQ_PRI_SHIFT			0x0
+#define IPQ5332_EDMA_DMAR_BURST_LEN_MASK		0x1
+#define IPQ5332_EDMA_DMAR_BURST_LEN_SHIFT		3
+#define IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK	0x1f
+#define IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT	4
+#define IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK	0x7
+#define IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT	9
+#define IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK	0x7
+#define IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT	12

-#define DEVSOC_EDMA_DMAR_REQ_PRI_SET(x) (((x) & DEVSOC_EDMA_DMAR_REQ_PRI_MASK) \
-					 << DEVSOC_EDMA_DMAR_REQ_PRI_SHIFT)
-#define DEVSOC_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(x) (((x) & DEVSOC_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK) \
-					 << DEVSOC_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT)
-#define DEVSOC_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(x) (((x) & DEVSOC_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK) \
-					 << DEVSOC_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT)
-#define DEVSOC_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(x) (((x) & DEVSOC_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK) \
-					 << DEVSOC_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT)
-#define DEVSOC_EDMA_DMAR_BURST_LEN_SET(x) (((x) & DEVSOC_EDMA_DMAR_BURST_LEN_MASK) \
-					 << DEVSOC_EDMA_DMAR_BURST_LEN_SHIFT)
+#define IPQ5332_EDMA_DMAR_REQ_PRI_SET(x) (((x) & IPQ5332_EDMA_DMAR_REQ_PRI_MASK) \
+					 << IPQ5332_EDMA_DMAR_REQ_PRI_SHIFT)
+#define IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(x) (((x) & IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK) \
+					 << IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT)
+#define IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(x) (((x) & IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK) \
+					 << IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT)
+#define IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(x) (((x) & IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK) \
+					 << IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT)
+#define IPQ5332_EDMA_DMAR_BURST_LEN_SET(x) (((x) & IPQ5332_EDMA_DMAR_BURST_LEN_MASK) \
+					 << IPQ5332_EDMA_DMAR_BURST_LEN_SHIFT)

-#define DEVSOC_EDMA_BURST_LEN_ENABLE			0x0
+#define IPQ5332_EDMA_BURST_LEN_ENABLE			0x0

 /*
 * EDMA_REG_PORT_CTRL register
 */
-#define DEVSOC_EDMA_PORT_CTRL_EN			0x3
+#define IPQ5332_EDMA_PORT_CTRL_EN			0x3

 /*
 * EDMA_REG_TXDESC_PROD_IDX register
 */
-#define DEVSOC_EDMA_TXDESC_PROD_IDX_MASK		0xffff
+#define IPQ5332_EDMA_TXDESC_PROD_IDX_MASK		0xffff

 /*
 * EDMA_REG_TXDESC_CONS_IDX register
 */
-#define DEVSOC_EDMA_TXDESC_CONS_IDX_MASK		0xffff
+#define IPQ5332_EDMA_TXDESC_CONS_IDX_MASK		0xffff

 /*
 * EDMA_REG_TXDESC_RING_SIZE register
 */
-#define DEVSOC_EDMA_TXDESC_RING_SIZE_MASK		0xffff
+#define IPQ5332_EDMA_TXDESC_RING_SIZE_MASK		0xffff

 /*
 * EDMA_REG_TXDESC_CTRL register
 */
-#define DEVSOC_EDMA_TXDESC_TX_EN			0x1
+#define IPQ5332_EDMA_TXDESC_TX_EN			0x1

 /*
 * EDMA_REG_TXCMPL_PROD_IDX register
 */
-#define DEVSOC_EDMA_TXCMPL_PROD_IDX_MASK		0xffff
+#define IPQ5332_EDMA_TXCMPL_PROD_IDX_MASK		0xffff

 /*
 * EDMA_REG_TXCMPL_CONS_IDX register
 */
-#define DEVSOC_EDMA_TXCMPL_CONS_IDX_MASK		0xffff
+#define IPQ5332_EDMA_TXCMPL_CONS_IDX_MASK		0xffff

 /*
 * EDMA_REG_TX_INT_CTRL register
 */
-#define DEVSOC_EDMA_TX_INT_MASK			0x3
+#define IPQ5332_EDMA_TX_INT_MASK			0x3

 /*
 * EDMA_REG_RXFILL_PROD_IDX register
 */
-#define DEVSOC_EDMA_RXFILL_PROD_IDX_MASK		0xffff
+#define IPQ5332_EDMA_RXFILL_PROD_IDX_MASK		0xffff

 /*
 * EDMA_REG_RXFILL_CONS_IDX register
 */
-#define DEVSOC_EDMA_RXFILL_CONS_IDX_MASK		0xffff
+#define IPQ5332_EDMA_RXFILL_CONS_IDX_MASK		0xffff

 /*
 * EDMA_REG_RXFILL_RING_SIZE register
 */
-#define DEVSOC_EDMA_RXFILL_RING_SIZE_MASK		0xffff
-#define DEVSOC_EDMA_RXFILL_BUF_SIZE_MASK		0xffff0000
-#define DEVSOC_EDMA_RXFILL_BUF_SIZE_SHIFT		16
+#define IPQ5332_EDMA_RXFILL_RING_SIZE_MASK		0xffff
+#define IPQ5332_EDMA_RXFILL_BUF_SIZE_MASK		0xffff0000
+#define IPQ5332_EDMA_RXFILL_BUF_SIZE_SHIFT		16

 /*
 * EDMA_REG_RXFILL_RING_EN register
 */
-#define DEVSOC_EDMA_RXFILL_RING_EN			0x1
+#define IPQ5332_EDMA_RXFILL_RING_EN			0x1

 /*
 * EDMA_REG_RXFILL_INT_MASK register
 */
-#define DEVSOC_EDMA_RXFILL_INT_MASK			0x1
+#define IPQ5332_EDMA_RXFILL_INT_MASK			0x1

 /*
 * EDMA_REG_RXDESC_PROD_IDX register
 */
-#define DEVSOC_EDMA_RXDESC_PROD_IDX_MASK		0xffff
+#define IPQ5332_EDMA_RXDESC_PROD_IDX_MASK		0xffff

 /*
 * EDMA_REG_RXDESC_CONS_IDX register
 */
-#define DEVSOC_EDMA_RXDESC_CONS_IDX_MASK		0xffff
+#define IPQ5332_EDMA_RXDESC_CONS_IDX_MASK		0xffff

 /*
 * EDMA_REG_RXDESC_RING_SIZE register
 */
-#define DEVSOC_EDMA_RXDESC_RING_SIZE_MASK		0xffff
-#define DEVSOC_EDMA_RXDESC_PL_OFFSET_MASK		0x1ff
-#define DEVSOC_EDMA_RXDESC_PL_OFFSET_SHIFT		16
+#define IPQ5332_EDMA_RXDESC_RING_SIZE_MASK		0xffff
+#define IPQ5332_EDMA_RXDESC_PL_OFFSET_MASK		0x1ff
+#define IPQ5332_EDMA_RXDESC_PL_OFFSET_SHIFT		16

 /*
 * EDMA_REG_RXDESC_CTRL register
 */
-#define DEVSOC_EDMA_RXDESC_RX_EN			0x1
+#define IPQ5332_EDMA_RXDESC_RX_EN			0x1

 /*
 * EDMA_REG_TX_INT_MASK register
 */
-#define DEVSOC_EDMA_TX_INT_MASK_PKT_INT		0x1
-#define DEVSOC_EDMA_TX_INT_MASK_UGT_INT		0x2
+#define IPQ5332_EDMA_TX_INT_MASK_PKT_INT		0x1
+#define IPQ5332_EDMA_TX_INT_MASK_UGT_INT		0x2

 /*
 * EDMA_REG_RXDESC_INT_MASK register
 */
-#define DEVSOC_EDMA_RXDESC_INT_MASK_PKT_INT		0x1
-#define DEVSOC_EDMA_MASK_INT_DISABLE			0x0
+#define IPQ5332_EDMA_RXDESC_INT_MASK_PKT_INT		0x1
+#define IPQ5332_EDMA_MASK_INT_DISABLE			0x0

 /*
 * TXDESC shift values
 */
-#define DEVSOC_EDMA_TXDESC_DATA_OFFSET_SHIFT		0
-#define DEVSOC_EDMA_TXDESC_DATA_OFFSET_MASK		0xfff
+#define IPQ5332_EDMA_TXDESC_DATA_OFFSET_SHIFT		0
+#define IPQ5332_EDMA_TXDESC_DATA_OFFSET_MASK		0xfff

-#define DEVSOC_EDMA_TXDESC_DATA_LENGTH_SHIFT		0
-#define DEVSOC_EDMA_TXDESC_DATA_LENGTH_MASK		0x1ffff
+#define IPQ5332_EDMA_TXDESC_DATA_LENGTH_SHIFT		0
+#define IPQ5332_EDMA_TXDESC_DATA_LENGTH_MASK		0x1ffff

-#define DEVSOC_EDMA_DST_PORT_TYPE			2
-#define DEVSOC_EDMA_DST_PORT_TYPE_SHIFT		28
-#define DEVSOC_EDMA_DST_PORT_TYPE_MASK			(0xf << DEVSOC_EDMA_DST_PORT_TYPE_SHIFT)
-#define DEVSOC_EDMA_DST_PORT_ID_SHIFT			16
-#define DEVSOC_EDMA_DST_PORT_ID_MASK			(0xfff << DEVSOC_EDMA_DST_PORT_ID_SHIFT)
+#define IPQ5332_EDMA_DST_PORT_TYPE			2
+#define IPQ5332_EDMA_DST_PORT_TYPE_SHIFT		28
+#define IPQ5332_EDMA_DST_PORT_TYPE_MASK			(0xf << IPQ5332_EDMA_DST_PORT_TYPE_SHIFT)
+#define IPQ5332_EDMA_DST_PORT_ID_SHIFT			16
+#define IPQ5332_EDMA_DST_PORT_ID_MASK			(0xfff << IPQ5332_EDMA_DST_PORT_ID_SHIFT)

-#define DEVSOC_EDMA_DST_PORT_TYPE_SET(x)		(((x) << DEVSOC_EDMA_DST_PORT_TYPE_SHIFT) & DEVSOC_EDMA_DST_PORT_TYPE_MASK)
-#define DEVSOC_EDMA_DST_PORT_ID_SET(x)			(((x) << EDMA_DST_PORT_ID_SHIFT) & EDMA_DST_PORT_ID_MASK)
+#define IPQ5332_EDMA_DST_PORT_TYPE_SET(x)		(((x) << IPQ5332_EDMA_DST_PORT_TYPE_SHIFT) & IPQ5332_EDMA_DST_PORT_TYPE_MASK)
+#define IPQ5332_EDMA_DST_PORT_ID_SET(x)			(((x) << EDMA_DST_PORT_ID_SHIFT) & EDMA_DST_PORT_ID_MASK)

-#define DEVSOC_EDMA_RXDESC_SRCINFO_TYPE_PORTID		0x2000
-#define DEVSOC_EDMA_RXDESC_SRCINFO_TYPE_SHIFT		8
-#define DEVSOC_EDMA_RXDESC_SRCINFO_TYPE_MASK		0xf000
-#define DEVSOC_EDMA_RXDESC_PORTNUM_BITS		0x0FFF
+#define IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_PORTID		0x2000
+#define IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_SHIFT		8
+#define IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_MASK		0xf000
+#define IPQ5332_EDMA_RXDESC_PORTNUM_BITS		0x0FFF

-#define DEVSOC_EDMA_RING_DMA_MASK			0xffffffff
+#define IPQ5332_EDMA_RING_DMA_MASK			0xffffffff

 /*
 * RXDESC shift values
 */
-#define DEVSOC_EDMA_RXDESC_PKT_SIZE_MASK		0x3ffff
-#define DEVSOC_EDMA_RXDESC_PKT_SIZE_SHIFT		0
-#define DEVSOC_EDMA_RXDESC_SRC_INFO_GET(x)		(x & 0xFFFF)
-#define DEVSOC_EDMA_RXDESC_RING_INT_STATUS_MASK	0x3
-#define DEVSOC_EDMA_RXFILL_RING_INT_STATUS_MASK	0x1
+#define IPQ5332_EDMA_RXDESC_PKT_SIZE_MASK		0x3ffff
+#define IPQ5332_EDMA_RXDESC_PKT_SIZE_SHIFT		0
+#define IPQ5332_EDMA_RXDESC_SRC_INFO_GET(x)		(x & 0xFFFF)
+#define IPQ5332_EDMA_RXDESC_RING_INT_STATUS_MASK	0x3
+#define IPQ5332_EDMA_RXFILL_RING_INT_STATUS_MASK	0x1

-#define DEVSOC_EDMA_TXCMPL_RING_INT_STATUS_MASK	0x3
-#define DEVSOC_EDMA_TXCMPL_RETMODE_OPAQUE		0x0
-#define DEVSOC_EDMA_TX_NE_INT_EN			0x2
-#define DEVSOC_EDMA_RX_NE_INT_EN			0x2
-#define DEVSOC_EDMA_TX_INITIAL_PROD_IDX		0x0
+#define IPQ5332_EDMA_TXCMPL_RING_INT_STATUS_MASK	0x3
+#define IPQ5332_EDMA_TXCMPL_RETMODE_OPAQUE		0x0
+#define IPQ5332_EDMA_TX_NE_INT_EN			0x2
+#define IPQ5332_EDMA_RX_NE_INT_EN			0x2
+#define IPQ5332_EDMA_TX_INITIAL_PROD_IDX		0x0

 #endif /*  __EDMA_REGS__ */
--- a/arch/arm/include/asm/arch-qca-common/clk.h
+++ b/arch/arm/include/asm/arch-qca-common/clk.h
@ -30,7 +30,7 @@
 #define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR		0x1803004
 #define GCC_BLSP1_QUP2_I2C_APPS_CBCR			0x1803010

-#else	// IPQ9574, devsoc
+#else	// IPQ9574, ipq5332

 #define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR		0x1802018
 #define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR		0x180201C
--- a/arch/arm/include/asm/arch-qca-common/qca_common.h
+++ b/arch/arm/include/asm/arch-qca-common/qca_common.h
@ -22,8 +22,8 @@
 #include <asm/arch-ipq5018/clk.h>
 #endif

-#ifdef CONFIG_ARCH_DEVSOC
-#include <asm/arch-devsoc/clk.h>
+#ifdef CONFIG_ARCH_IPQ5332
+#include <asm/arch-ipq5332/clk.h>
 #endif

 #ifdef CONFIG_ARCH_IPQ6018
--- a/arch/arm/include/asm/arch-qca-common/qpic_nand.h
+++ b/arch/arm/include/asm/arch-qca-common/qpic_nand.h
@ -32,7 +32,7 @@

 #if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI) \
 	|| defined(CONFIG_IPQ6018) || defined(CONFIG_IPQ5018) \
-	|| defined(CONFIG_DEVSOC) || defined(CONFIG_IPQ9574)
+	|| defined(CONFIG_IPQ5332) || defined(CONFIG_IPQ9574)
 #define QPIC_EBI2ND_BASE		(0x079b0000)
 #else
 #error "QPIC NAND not supported"
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@ -1174,7 +1174,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_IPQ9574_AP_AL02_C16	0x8050F01
 #define MACH_TYPE_IPQ9574_AP_AL03_C1	0x8050002
 #define MACH_TYPE_IPQ9574_AP_AL03_C2	0x8050102
-#define MACH_TYPE_DEVSOC_EMULATION	0xF060000
+#define MACH_TYPE_IPQ5332_EMULATION	0xF060000

 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
--- a/board/ipq5332/Kconfig
+++ b/board/ipq5332/Kconfig
@ -1,16 +1,16 @@
-if ARCH_DEVSOC
+if ARCH_IPQ5332

 config SYS_CPU
-       default "devsoc"
+       default "ipq5332"

 config SYS_BOARD
-       default "devsoc"
+       default "ipq5332"

 config SYS_VENDOR
       default "qca/arm"

 config SYS_CONFIG_NAME
-       default "devsoc"
+       default "ipq5332"

 config NAND_FLASH
 	bool "Enable NAND Framework"
--- a/board/qca/arm/common/board_init.c
+++ b/board/qca/arm/common/board_init.c
@ -253,7 +253,7 @@ int board_init(void)
 		printf("WARN: ipq_board_usb_init failed\n");
 	}

-#if defined(CONFIG_IPQ9574_EDMA) || defined(CONFIG_DEVSOC_EDMA)
+#if defined(CONFIG_IPQ9574_EDMA) || defined(CONFIG_IPQ5332_EDMA)
 	aquantia_phy_reset_init();
 #endif
 	disable_audio_clks();
--- a/board/qca/arm/common/cmd_bootqca.c
+++ b/board/qca/arm/common/cmd_bootqca.c
@ -890,7 +890,7 @@ static int do_bootipq(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])

 	ret = qca_scm_call(SCM_SVC_FUSE, QFPROM_IS_AUTHENTICATE_CMD, &buf, sizeof(char));

-#if defined(CONFIG_IPQ9574_EDMA) || defined(CONFIG_DEVSOC_EDMA)
+#if defined(CONFIG_IPQ9574_EDMA) || defined(CONFIG_IPQ5332_EDMA)
 	aquantia_phy_reset_init_done();
 #endif
 	/*
--- a/board/qca/arm/common/fdt_fixup.c
+++ b/board/qca/arm/common/fdt_fixup.c
@ -1075,7 +1075,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 		{ "qcom,ebi2-nandc-bam-v2.1.1", MTD_DEV_TYPE_NAND, 0 },
 		{ "qcom,ipq9574-nand", MTD_DEV_TYPE_NAND, 0 },
 		{ "qcom,ipq8074-nand", MTD_DEV_TYPE_NAND, 0 },
-		{ "qcom,devsoc-nand", MTD_DEV_TYPE_NAND, 0 },
+		{ "qcom,ipq5332-nand", MTD_DEV_TYPE_NAND, 0 },
 		{ "spinand,mt29f", MTD_DEV_TYPE_NAND, 1 },
 		{ "n25q128a11", MTD_DEV_TYPE_NAND,
 				CONFIG_IPQ_SPI_NOR_INFO_IDX },
--- a/board/qca/arm/ipq5332/Makefile
+++ b/board/qca/arm/ipq5332/Makefile
@ -1,4 +1,4 @@
-ccflags-y += -I$(srctree)/board/qca/arm/devsoc
-cppflags-y += -I$(srctree)/board/qca/arm/devsoc
-obj-y   := devsoc.o
+ccflags-y += -I$(srctree)/board/qca/arm/ipq5332
+cppflags-y += -I$(srctree)/board/qca/arm/ipq5332
+obj-y   := ipq5332.o
 obj-y   += clock.o
--- a/board/qca/arm/ipq5332/clock.c
+++ b/board/qca/arm/ipq5332/clock.c
@ -14,7 +14,7 @@
 */

 #include <common.h>
-#include <asm/arch-devsoc/clk.h>
+#include <asm/arch-ipq5332/clk.h>
 #include <asm/io.h>
 #include <asm/errno.h>

@ -332,7 +332,7 @@ void usb_clock_deinit(void)
 }
 #endif

-#ifdef CONFIG_DEVSOC_EDMA
+#ifdef CONFIG_IPQ5332_EDMA
 void nssnoc_init(void){
 	unsigned int gcc_qdss_at_cmd_rcgr_addr = 0x182D004;

--- a/board/qca/arm/ipq5332/ipq5332.c
+++ b/board/qca/arm/ipq5332/ipq5332.c
@ -23,7 +23,7 @@
 #include <asm/arch-qca-common/uart.h>
 #include <asm/arch-qca-common/scm.h>
 #include <asm/arch-qca-common/iomap.h>
-#include <devsoc.h>
+#include <ipq5332.h>
 #ifdef CONFIG_QPIC_NAND
 #include <asm/arch-qca-common/qpic_nand.h>
 #include <nand.h>
@ -40,7 +40,7 @@
 DECLARE_GLOBAL_DATA_PTR;

 static int aq_phy_initialised = 0;
-extern int devsoc_edma_init(void *cfg);
+extern int ipq5332_edma_init(void *cfg);
 extern int ipq_spi_init(u16);

 const char *rsvd_node = "/reserved-memory";
@ -123,7 +123,7 @@ void fdt_fixup_flash(void *blob)
 	int node_off, ret;
 	char *flash = "/soc/nand@79b0000";

-	if (gd->bd->bi_arch_number == MACH_TYPE_DEVSOC_EMULATION)
+	if (gd->bd->bi_arch_number == MACH_TYPE_IPQ5332_EMULATION)
 		return;

 	node_off = fdt_path_offset(gd->fdt_blob, "nand");
@ -148,7 +148,7 @@ void ipq_uboot_fdt_fixup(void)
 	void *blob = (void *)gd->fdt_blob;
 	ulong machid = gd->bd->bi_arch_number;

-	if (machid == MACH_TYPE_DEVSOC_EMULATION)
+	if (machid == MACH_TYPE_IPQ5332_EMULATION)
 		return;

 	/* fix peripherals required for basic board bring up
@ -268,7 +268,7 @@ void sdhci_bus_pwr_off(struct sdhci_host *host)

 __weak void board_mmc_deinit(void)
 {
-	/*since we do not have misc register in devsoc
+	/*since we do not have misc register in ipq5332
 	 * so simply return from this function
 	 */
 	return;
@ -653,7 +653,7 @@ __weak int ipq_get_tz_version(char *version_name, int buf_size)

 int apps_iscrashed_crashdump_disabled(void)
 {
-	u32 *dmagic = (u32 *)CONFIG_DEVSOC_DMAGIC_ADDR;
+	u32 *dmagic = (u32 *)CONFIG_IPQ5332_DMAGIC_ADDR;

 	if (*dmagic & DLOAD_DISABLED)
 		return 1;
@ -663,7 +663,7 @@ int apps_iscrashed_crashdump_disabled(void)

 int apps_iscrashed(void)
 {
-	u32 *dmagic = (u32 *)CONFIG_DEVSOC_DMAGIC_ADDR;
+	u32 *dmagic = (u32 *)CONFIG_IPQ5332_DMAGIC_ADDR;

 	if (*dmagic & DLOAD_MAGIC_COOKIE)
 		return 1;
@ -766,7 +766,7 @@ void set_flash_secondary_type(qca_smem_flash_info_t *smem)
 	return;
 };

-#ifdef CONFIG_DEVSOC_EDMA
+#ifdef CONFIG_IPQ5332_EDMA
 int get_mdc_mdio_gpio(int mdc_mdio_gpio[2])
 {
 	int mdc_mdio_gpio_cnt = 2, node;
@ -914,7 +914,7 @@ void bring_phy_out_of_reset(void)
 	mdelay(500);
 }

-void devsoc_eth_initialize(void)
+void ipq5332_eth_initialize(void)
 {
 	eth_clock_init();

@ -927,11 +927,11 @@ int board_eth_init(bd_t *bis)
 {
 	int ret = 0;

-	devsoc_eth_initialize();
+	ipq5332_eth_initialize();

-	ret = devsoc_edma_init(NULL);
+	ret = ipq5332_edma_init(NULL);
 	if (ret != 0)
-		printf("%s: devsoc_edma_init failed : %d\n", __func__, ret);
+		printf("%s: ipq5332_edma_init failed : %d\n", __func__, ret);

 	return ret;
 }
--- a/board/qca/arm/ipq5332/ipq5332.h
+++ b/board/qca/arm/ipq5332/ipq5332.h
@ -13,10 +13,10 @@
 * GNU General Public License for more details.
 */

-#ifndef _DEVSOC_CDP_H_
-#define _DEVSOC_CDP_H_
+#ifndef _IPQ5332_CDP_H_
+#define _IPQ5332_CDP_H_

-#include <configs/devsoc.h>
+#include <configs/ipq5332.h>
 #include <asm/u-boot.h>
 #include <asm/arch-qca-common/qca_common.h>
 #include "phy.h"
@ -41,7 +41,7 @@ extern const add_node_t add_fdt_node[];

 #define USB30_GUCTL				0x8A0C12C

-#define CONFIG_DEVSOC_DMAGIC_ADDR		0x193D100
+#define CONFIG_IPQ5332_DMAGIC_ADDR		0x193D100
 #define DLOAD_MAGIC_COOKIE			0x10
 #define DLOAD_DISABLED				0x40
 #define DLOAD_BITS				0xFF
@ -283,4 +283,4 @@ void pcie_reset(int pcie_id);
 #endif
 unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int,
 					 unsigned int, unsigned int);
-#endif /* _DEVSOC_CDP_H_ */
+#endif /* _IPQ5332_CDP_H_ */
--- a/configs/devsoc_defconfig
+++ b/configs/devsoc_defconfig
@ -12,7 +12,7 @@
 CONFIG_ARM=y
 CONFIG_HAS_VBAR=y
 CONFIG_CPU_V7=y
-CONFIG_ARCH_DEVSOC=y
+CONFIG_ARCH_IPQ5332=y
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_SYS_MALLOC_F=y
 CONFIG_DM_SERIAL=y
@ -26,7 +26,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 # CONFIG_FIT_SIGNATURE is not set
 CONFIG_SYS_EXTRA_OPTIONS=""
-CONFIG_SYS_PROMPT="devsoc# "
+CONFIG_SYS_PROMPT="ipq5332# "

 #
 # Tiny support
--- a/configs/devsoc_tiny_debug_defconfig
+++ b/configs/devsoc_tiny_debug_defconfig
@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_HAS_VBAR=y
 CONFIG_CPU_V7=y
-CONFIG_ARCH_DEVSOC=y
+CONFIG_ARCH_IPQ5332=y
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_SYS_MALLOC_F=y
 CONFIG_DM_SERIAL=y
@ -15,7 +15,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 # CONFIG_FIT_SIGNATURE is not set
 CONFIG_SYS_EXTRA_OPTIONS=""
-CONFIG_SYS_PROMPT="devsoc# "
+CONFIG_SYS_PROMPT="ipq5332# "

 #
 # Tiny support
--- a/configs/devsoc_tiny_defconfig
+++ b/configs/devsoc_tiny_defconfig
@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_HAS_VBAR=y
 CONFIG_CPU_V7=y
-CONFIG_ARCH_DEVSOC=y
+CONFIG_ARCH_IPQ5332=y
 CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_SYS_MALLOC_F=y
 CONFIG_DM_SERIAL=y
@ -15,7 +15,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 # CONFIG_FIT_SIGNATURE is not set
 CONFIG_SYS_EXTRA_OPTIONS=""
-CONFIG_SYS_PROMPT="devsoc# "
+CONFIG_SYS_PROMPT="ipq5332# "

 #
 # Tiny support
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@ -9,7 +9,7 @@ obj-$(CONFIG_ARCH_IPQ807x) += ipq_gpio.o
 obj-$(CONFIG_ARCH_IPQ806x) += ipq_gpio.o
 obj-$(CONFIG_ARCH_IPQ40xx) += ipq_gpio.o
 obj-$(CONFIG_ARCH_IPQ5018) += ipq_gpio.o
-obj-$(CONFIG_ARCH_DEVSOC) += ipq_gpio.o
+obj-$(CONFIG_ARCH_IPQ5332) += ipq_gpio.o
 obj-$(CONFIG_ARCH_IPQ6018) += ipq_gpio.o
 obj-$(CONFIG_ARCH_IPQ9574) += ipq_gpio.o
 ifndef CONFIG_SPL_BUILD
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@ -93,11 +93,11 @@ obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/ipq5018_gmac.o
 obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/ipq5018_uniphy.o
 obj-$(CONFIG_IPQ5018_MDIO) += ipq5018/ipq5018_mdio.o
 obj-$(CONFIG_IPQ5018_GMAC) += ipq5018/athrs17_phy.o
-obj-$(CONFIG_DEVSOC_EDMA) += devsoc/devsoc_edma.o
-obj-$(CONFIG_DEVSOC_EDMA) += devsoc/devsoc_ppe.o
+obj-$(CONFIG_IPQ5332_EDMA) += ipq5332/ipq5332_edma.o
+obj-$(CONFIG_IPQ5332_EDMA) += ipq5332/ipq5332_ppe.o

-ifndef CONFIG_DEVSOC_RUMI
-obj-$(CONFIG_DEVSOC_EDMA) += devsoc/devsoc_uniphy.o
+ifndef CONFIG_IPQ5332_RUMI
+obj-$(CONFIG_IPQ5332_EDMA) += ipq5332/ipq5332_uniphy.o
 endif

 obj-$(CONFIG_IPQ_MDIO) += ipq_common/ipq_mdio.o
--- a/drivers/net/ipq5332/ipq5332_edma.c
+++ b/drivers/net/ipq5332/ipq5332_edma.c
--- a/drivers/net/ipq5332/ipq5332_edma.h
+++ b/drivers/net/ipq5332/ipq5332_edma.h
@ -17,75 +17,75 @@
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 **************************************************************************
 */
-#ifndef __DEVSOC_EDMA__
-#define __DEVSOC_EDMA__
+#ifndef __IPQ5332_EDMA__
+#define __IPQ5332_EDMA__

-#define DEVSOC_NSS_DP_START_PHY_PORT   1
-#define DEVSOC_NSS_DP_MAX_PHY_PORTS    2
+#define IPQ5332_NSS_DP_START_PHY_PORT   1
+#define IPQ5332_NSS_DP_MAX_PHY_PORTS    2

-#define DEVSOC_EDMA_DEVICE_NODE_NAME	"edma"
+#define IPQ5332_EDMA_DEVICE_NODE_NAME	"edma"

 /* Number of descriptors in each ring is defined with below macro */
-#define DEVSOC_EDMA_TX_RING_SIZE	128
-#define DEVSOC_EDMA_RX_RING_SIZE	128
+#define IPQ5332_EDMA_TX_RING_SIZE	128
+#define IPQ5332_EDMA_RX_RING_SIZE	128

 /* Number of byte in a descriptor is defined with below macros for each of
 * the rings respectively */
-#define DEVSOC_EDMA_TXDESC_DESC_SIZE	(sizeof(struct devsoc_edma_txdesc_desc))
-#define DEVSOC_EDMA_TXCMPL_DESC_SIZE	(sizeof(struct devsoc_edma_txcmpl_desc))
-#define DEVSOC_EDMA_RXDESC_DESC_SIZE	(sizeof(struct devsoc_edma_rxdesc_desc))
-#define DEVSOC_EDMA_RXFILL_DESC_SIZE	(sizeof(struct devsoc_edma_rxfill_desc))
-#define DEVSOC_EDMA_RX_SEC_DESC_SIZE	(sizeof(struct devsoc_edma_rx_sec_desc))
-#define DEVSOC_EDMA_TX_SEC_DESC_SIZE	(sizeof(struct devsoc_edma_tx_sec_desc))
+#define IPQ5332_EDMA_TXDESC_DESC_SIZE	(sizeof(struct ipq5332_edma_txdesc_desc))
+#define IPQ5332_EDMA_TXCMPL_DESC_SIZE	(sizeof(struct ipq5332_edma_txcmpl_desc))
+#define IPQ5332_EDMA_RXDESC_DESC_SIZE	(sizeof(struct ipq5332_edma_rxdesc_desc))
+#define IPQ5332_EDMA_RXFILL_DESC_SIZE	(sizeof(struct ipq5332_edma_rxfill_desc))
+#define IPQ5332_EDMA_RX_SEC_DESC_SIZE	(sizeof(struct ipq5332_edma_rx_sec_desc))
+#define IPQ5332_EDMA_TX_SEC_DESC_SIZE	(sizeof(struct ipq5332_edma_tx_sec_desc))

-#define DEVSOC_EDMA_START_GMACS	DEVSOC_NSS_DP_START_PHY_PORT
-#define DEVSOC_EDMA_MAX_GMACS		DEVSOC_NSS_DP_MAX_PHY_PORTS
+#define IPQ5332_EDMA_START_GMACS	IPQ5332_NSS_DP_START_PHY_PORT
+#define IPQ5332_EDMA_MAX_GMACS		IPQ5332_NSS_DP_MAX_PHY_PORTS

-#define DEVSOC_EDMA_TX_BUFF_SIZE	2048
-#define DEVSOC_EDMA_RX_BUFF_SIZE	2048
+#define IPQ5332_EDMA_TX_BUFF_SIZE	2048
+#define IPQ5332_EDMA_RX_BUFF_SIZE	2048

 /* Max number of rings of each type is defined with below macro */
-#define DEVSOC_EDMA_MAX_TXCMPL_RINGS	24	/* Max TxCmpl rings */
-#define DEVSOC_EDMA_MAX_TXDESC_RINGS	24	/* Max TxDesc rings */
-#define DEVSOC_EDMA_MAX_RXDESC_RINGS	16	/* Max RxDesc rings */
-#define DEVSOC_EDMA_MAX_RXFILL_RINGS	8	/* Max RxFill rings */
+#define IPQ5332_EDMA_MAX_TXCMPL_RINGS	24	/* Max TxCmpl rings */
+#define IPQ5332_EDMA_MAX_TXDESC_RINGS	24	/* Max TxDesc rings */
+#define IPQ5332_EDMA_MAX_RXDESC_RINGS	16	/* Max RxDesc rings */
+#define IPQ5332_EDMA_MAX_RXFILL_RINGS	8	/* Max RxFill rings */

-#define DEVSOC_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
-#define DEVSOC_EDMA_RXFILL_DESC(R, i) 	DEVSOC_EDMA_GET_DESC(R, i, struct devsoc_edma_rxfill_desc)
-#define DEVSOC_EDMA_RXDESC_DESC(R, i) 	DEVSOC_EDMA_GET_DESC(R, i, struct devsoc_edma_rxdesc_desc)
-#define DEVSOC_EDMA_TXDESC_DESC(R, i) 	DEVSOC_EDMA_GET_DESC(R, i, struct devsoc_edma_txdesc_desc)
-#define DEVSOC_EDMA_TXCMPL_DESC(R, i) 	DEVSOC_EDMA_GET_DESC(R, i, struct devsoc_edma_txcmpl_desc)
+#define IPQ5332_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
+#define IPQ5332_EDMA_RXFILL_DESC(R, i) 	IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_rxfill_desc)
+#define IPQ5332_EDMA_RXDESC_DESC(R, i) 	IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_rxdesc_desc)
+#define IPQ5332_EDMA_TXDESC_DESC(R, i) 	IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_txdesc_desc)
+#define IPQ5332_EDMA_TXCMPL_DESC(R, i) 	IPQ5332_EDMA_GET_DESC(R, i, struct ipq5332_edma_txcmpl_desc)

-#define DEVSOC_EDMA_DEV		1
+#define IPQ5332_EDMA_DEV		1

 /* Only 1 ring of each type will be used in U-Boot which is defined with
 * below macros */
-#define DEVSOC_EDMA_TX_DESC_RING_START	23
-#define DEVSOC_EDMA_TX_DESC_RING_NOS	1
-#define DEVSOC_EDMA_TX_DESC_RING_SIZE	\
-(DEVSOC_EDMA_TX_DESC_RING_START + DEVSOC_EDMA_TX_DESC_RING_NOS)
+#define IPQ5332_EDMA_TX_DESC_RING_START	23
+#define IPQ5332_EDMA_TX_DESC_RING_NOS	1
+#define IPQ5332_EDMA_TX_DESC_RING_SIZE	\
+(IPQ5332_EDMA_TX_DESC_RING_START + IPQ5332_EDMA_TX_DESC_RING_NOS)

-#define DEVSOC_EDMA_TX_CMPL_RING_START	23
-#define DEVSOC_EDMA_TX_CMPL_RING_NOS	1
-#define DEVSOC_EDMA_TX_CMPL_RING_SIZE	\
-(DEVSOC_EDMA_TX_CMPL_RING_START + DEVSOC_EDMA_TX_CMPL_RING_NOS)
+#define IPQ5332_EDMA_TX_CMPL_RING_START	23
+#define IPQ5332_EDMA_TX_CMPL_RING_NOS	1
+#define IPQ5332_EDMA_TX_CMPL_RING_SIZE	\
+(IPQ5332_EDMA_TX_CMPL_RING_START + IPQ5332_EDMA_TX_CMPL_RING_NOS)

-#define DEVSOC_EDMA_RX_DESC_RING_START	15
-#define DEVSOC_EDMA_RX_DESC_RING_NOS	1
-#define DEVSOC_EDMA_RX_DESC_RING_SIZE	\
-(DEVSOC_EDMA_RX_DESC_RING_START + DEVSOC_EDMA_RX_DESC_RING_NOS)
+#define IPQ5332_EDMA_RX_DESC_RING_START	15
+#define IPQ5332_EDMA_RX_DESC_RING_NOS	1
+#define IPQ5332_EDMA_RX_DESC_RING_SIZE	\
+(IPQ5332_EDMA_RX_DESC_RING_START + IPQ5332_EDMA_RX_DESC_RING_NOS)

-#define DEVSOC_EDMA_RX_FILL_RING_START	7
-#define DEVSOC_EDMA_RX_FILL_RING_NOS	1
-#define DEVSOC_EDMA_RX_FILL_RING_SIZE	\
-(DEVSOC_EDMA_RX_FILL_RING_START + DEVSOC_EDMA_RX_FILL_RING_NOS)
+#define IPQ5332_EDMA_RX_FILL_RING_START	7
+#define IPQ5332_EDMA_RX_FILL_RING_NOS	1
+#define IPQ5332_EDMA_RX_FILL_RING_SIZE	\
+(IPQ5332_EDMA_RX_FILL_RING_START + IPQ5332_EDMA_RX_FILL_RING_NOS)

 #define NETDEV_TX_BUSY	1

 /*
 * RxDesc descriptor
 */
-struct devsoc_edma_rxdesc_desc {
+struct ipq5332_edma_rxdesc_desc {
 	uint32_t rdes0; /* Contains buffer address */
 	uint32_t rdes1; /* Contains more bit, priority bit, service code */
 	uint32_t rdes2; /* Contains opaque */
@ -99,7 +99,7 @@ struct devsoc_edma_rxdesc_desc {
 /*
 * EDMA Rx Secondary Descriptor
 */
-struct devsoc_edma_rx_sec_desc {
+struct ipq5332_edma_rx_sec_desc {
 	uint32_t rx_sec0; /* Contains timestamp */
 	uint32_t rx_sec1; /* Contains secondary checksum status */
 	uint32_t rx_sec2; /* Contains QoS tag */
@ -113,7 +113,7 @@ struct devsoc_edma_rx_sec_desc {
 /*
 * RxFill descriptor
 */
-struct devsoc_edma_rxfill_desc {
+struct ipq5332_edma_rxfill_desc {
 	uint32_t rdes0; /* Contains buffer address */
 	uint32_t rdes1; /* Contains buffer size */
 	uint32_t rdes2; /* Contains opaque */
@ -123,7 +123,7 @@ struct devsoc_edma_rxfill_desc {
 /*
 * TxDesc descriptor
 */
-struct devsoc_edma_txdesc_desc {
+struct ipq5332_edma_txdesc_desc {
 	uint32_t tdes0; /* Low 32-bit of buffer address */
 	uint32_t tdes1; /* Buffer recycling, PTP tag flag, PRI valid flag */
 	uint32_t tdes2; /* Low 32-bit of opaque value */
@ -137,7 +137,7 @@ struct devsoc_edma_txdesc_desc {
 /*
 * EDMA Tx Secondary Descriptor
 */
-struct devsoc_edma_tx_sec_desc {
+struct ipq5332_edma_tx_sec_desc {
 	uint32_t tx_sec0; /* Reserved */
 	uint32_t tx_sec1; /* Custom csum offset, payload offset, TTL/NAT action */
 	uint32_t rx_sec2; /* NAPT translated port, DSCP value, TTL value */
@ -151,7 +151,7 @@ struct devsoc_edma_tx_sec_desc {
 /*
 * TxCmpl descriptor
 */
-struct devsoc_edma_txcmpl_desc {
+struct ipq5332_edma_txcmpl_desc {
 	uint32_t tdes0; /* Low 32-bit opaque value */
 	uint32_t tdes1; /* High 32-bit opaque value */
 	uint32_t tdes2; /* More fragment, transmit ring id, pool id */
@ -161,13 +161,13 @@ struct devsoc_edma_txcmpl_desc {
 /*
 * Tx descriptor ring
 */
-struct devsoc_edma_txdesc_ring {
+struct ipq5332_edma_txdesc_ring {
 	uint32_t prod_idx;		/* Producer index */
 	uint32_t avail_desc;		/* Number of available descriptor to process */
 	uint32_t id;			/* TXDESC ring number */
-	struct devsoc_edma_txdesc_desc *desc;	/* descriptor ring virtual address */
+	struct ipq5332_edma_txdesc_desc *desc;	/* descriptor ring virtual address */
 	dma_addr_t dma;			/* descriptor ring physical address */
-	struct devsoc_edma_tx_sec_desc *sdesc; /* Secondary descriptor ring virtual addr */
+	struct ipq5332_edma_tx_sec_desc *sdesc; /* Secondary descriptor ring virtual addr */
 	dma_addr_t sdma;		/* Secondary descriptor ring physical address */
 	uint16_t count;			/* number of descriptors */
 };
@ -175,10 +175,10 @@ struct devsoc_edma_txdesc_ring {
 /*
 * TxCmpl ring
 */
-struct devsoc_edma_txcmpl_ring {
+struct ipq5332_edma_txcmpl_ring {
 	uint32_t cons_idx;		/* Consumer index */
 	uint32_t avail_pkt;		/* Number of available packets to process */
-	struct devsoc_edma_txcmpl_desc *desc; /* descriptor ring virtual address */
+	struct ipq5332_edma_txcmpl_desc *desc; /* descriptor ring virtual address */
 	uint32_t id;			/* TXCMPL ring number */
 	dma_addr_t dma;			/* descriptor ring physical address */
 	uint32_t count;			/* Number of descriptors in the ring */
@ -187,29 +187,29 @@ struct devsoc_edma_txcmpl_ring {
 /*
 * RxFill ring
 */
-struct devsoc_edma_rxfill_ring {
+struct ipq5332_edma_rxfill_ring {
 	uint32_t id;			/* RXFILL ring number */
 	uint32_t count;			/* number of descriptors in the ring */
 	uint32_t prod_idx;		/* Ring producer index */
-	struct devsoc_edma_rxfill_desc *desc;  /* descriptor ring virtual address */
+	struct ipq5332_edma_rxfill_desc *desc;  /* descriptor ring virtual address */
 	dma_addr_t dma;			/* descriptor ring physical address */
 };

 /*
 * RxDesc ring
 */
-struct devsoc_edma_rxdesc_ring {
+struct ipq5332_edma_rxdesc_ring {
 	uint32_t id;			/* RXDESC ring number */
 	uint32_t count;			/* number of descriptors in the ring */
 	uint32_t cons_idx;		/* Ring consumer index */
-	struct devsoc_edma_rxdesc_desc *desc; /* Primary descriptor ring virtual addr */
-	struct devsoc_edma_sec_rxdesc_ring *sdesc; /* Secondary desc ring VA */
-	struct devsoc_edma_rxfill_ring *rxfill;	/* RXFILL ring used */
+	struct ipq5332_edma_rxdesc_desc *desc; /* Primary descriptor ring virtual addr */
+	struct ipq5332_edma_sec_rxdesc_ring *sdesc; /* Secondary desc ring VA */
+	struct ipq5332_edma_rxfill_ring *rxfill;	/* RXFILL ring used */
 	dma_addr_t dma;			/* Primary descriptor ring physical address */
 	dma_addr_t sdma;		/* Secondary descriptor ring physical address */
 };

-enum devsoc_edma_tx {
+enum ipq5332_edma_tx {
 	EDMA_TX_OK = 0,		/* Tx success */
 	EDMA_TX_DESC = 1,	/* Not enough descriptors */
 	EDMA_TX_FAIL = 2,	/* Tx failure */
@ -224,11 +224,11 @@ struct queue_per_cpu_info {
 	u32 rx_status; /* rx interrupt status */
 	u32 tx_start; /* tx queue start */
 	u32 rx_start; /* rx queue start */
-	struct devsoc_edma_common_info *c_info; /* edma common info */
+	struct ipq5332_edma_common_info *c_info; /* edma common info */
 };

 /* edma hw specific data */
-struct devsoc_edma_hw {
+struct ipq5332_edma_hw {
 	unsigned long  __iomem *hw_addr; /* inner register address */
 	u8 intr_clear_type; /* interrupt clear */
 	u8 intr_sw_idx_w; /* To do chk type interrupt software index */
@ -237,10 +237,10 @@ struct devsoc_edma_hw {
 	uint16_t rx_payload_offset; /* start of the payload offset */
 	uint32_t flags; /* internal flags */
 	int active; /* status */
-	struct devsoc_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */
-	struct devsoc_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */
-	struct devsoc_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */
-	struct devsoc_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */
+	struct ipq5332_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */
+	struct ipq5332_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */
+	struct ipq5332_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */
+	struct ipq5332_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */
 	uint32_t txdesc_rings; /* Number of TxDesc rings */
 	uint32_t txdesc_ring_start; /* Id of first TXDESC ring */
 	uint32_t txdesc_ring_end; /* Id of the last TXDESC ring */
@ -261,12 +261,12 @@ struct devsoc_edma_hw {
 	uint32_t misc_intr_mask; /* misc interrupt interrupt mask */
 };

-struct devsoc_edma_common_info {
-	struct devsoc_edma_hw hw;
+struct ipq5332_edma_common_info {
+	struct ipq5332_edma_hw hw;
 };

 #define MAX_PHY 6
-struct devsoc_eth_dev {
+struct ipq5332_eth_dev {
 	u8 *phy_address;
 	uint no_of_phys;
 	uint interface;
@ -278,12 +278,12 @@ struct devsoc_eth_dev {
 	int link_printed;
 	u32 padding;
 	struct eth_device *dev;
-	struct devsoc_edma_common_info *c_info;
+	struct ipq5332_edma_common_info *c_info;
 	struct phy_ops *ops[MAX_PHY];
 	const char phy_name[MDIO_NAME_LEN];
 } __attribute__ ((aligned(8)));

-static inline void* devsoc_alloc_mem(u32 size)
+static inline void* ipq5332_alloc_mem(u32 size)
 {
 	void *p = malloc(size);
 	if (p != NULL)
@ -291,7 +291,7 @@ static inline void* devsoc_alloc_mem(u32 size)
 	return p;
 }

-static inline void* devsoc_alloc_memalign(u32 size)
+static inline void* ipq5332_alloc_memalign(u32 size)
 {
 	void *p = memalign(CONFIG_SYS_CACHELINE_SIZE, size);
 	if (p != NULL)
@ -299,14 +299,14 @@ static inline void* devsoc_alloc_memalign(u32 size)
 	return p;
 }

-static inline void devsoc_free_mem(void *ptr)
+static inline void ipq5332_free_mem(void *ptr)
 {
 	if (ptr)
 		free(ptr);
 }

-uint32_t devsoc_edma_reg_read(uint32_t reg_off);
-void devsoc_edma_reg_write(uint32_t reg_off, uint32_t val);
+uint32_t ipq5332_edma_reg_read(uint32_t reg_off);
+void ipq5332_edma_reg_write(uint32_t reg_off, uint32_t val);


 extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs);
@ -314,28 +314,28 @@ extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs);
 typedef struct {
 	uint count;
 	u8 addr[7];
-} devsoc_edma_phy_addr_t;
+} ipq5332_edma_phy_addr_t;

-/* devsoc edma Paramaters */
+/* ipq5332 edma Paramaters */
 typedef struct {
 	uint base;
 	int unit;
 	uint mac_conn_to_phy;
 	phy_interface_t phy;
-	devsoc_edma_phy_addr_t phy_addr;
+	ipq5332_edma_phy_addr_t phy_addr;
 	char phy_name[MDIO_NAME_LEN];
-} devsoc_edma_board_cfg_t;
+} ipq5332_edma_board_cfg_t;

-extern void devsoc_ppe_provision_init(void);
-extern void devsoc_port_mac_clock_reset(int port);
-extern void devsoc_speed_clock_set(int port, int clk[4]);
-extern void devsoc_pqsgmii_speed_set(int port, int speed, int status);
-extern void devsoc_uxsgmii_speed_set(int port, int speed, int duplex, int status);
+extern void ipq5332_ppe_provision_init(void);
+extern void ipq5332_port_mac_clock_reset(int port);
+extern void ipq5332_speed_clock_set(int port, int clk[4]);
+extern void ipq5332_pqsgmii_speed_set(int port, int speed, int status);
+extern void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex, int status);
 extern void ppe_port_mux_mac_type_set(int port_id, int mode);
 extern void ppe_port_bridge_txmac_set(int port, int status);
-extern void devsoc_10g_r_speed_set(int port, int status);
+extern void ipq5332_10g_r_speed_set(int port, int status);
 extern int phy_status_get_from_ppe(int port_id);

-extern void devsoc_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny);
+extern void ipq5332_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny);
 extern void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode);
-#endif /* ___DEVSOC_EDMA__ */
+#endif /* ___IPQ5332_EDMA__ */
--- a/drivers/net/ipq5332/ipq5332_ppe.c
+++ b/drivers/net/ipq5332/ipq5332_ppe.c
@ -20,9 +20,9 @@

 #include <common.h>
 #include <asm/global_data.h>
-#include "devsoc_ppe.h"
-#ifndef CONFIG_DEVSOC_RUMI
-#include "devsoc_uniphy.h"
+#include "ipq5332_ppe.h"
+#ifndef CONFIG_IPQ5332_RUMI
+#include "ipq5332_uniphy.h"
 #endif
 #include <fdtdec.h>
 #include "ipq_phy.h"
@ -37,19 +37,19 @@ DECLARE_GLOBAL_DATA_PTR;
 #define pr_info(fmt, args...) printf(fmt, ##args);

 /*
- * devsoc_ppe_reg_read()
+ * ipq5332_ppe_reg_read()
 */
-static inline void devsoc_ppe_reg_read(u32 reg, u32 *val)
+static inline void ipq5332_ppe_reg_read(u32 reg, u32 *val)
 {
-	*val = readl((void *)(DEVSOC_PPE_BASE_ADDR + reg));
+	*val = readl((void *)(IPQ5332_PPE_BASE_ADDR + reg));
 }

 /*
- * devsoc_ppe_reg_write()
+ * ipq5332_ppe_reg_write()
 */
-static inline void devsoc_ppe_reg_write(u32 reg, u32 val)
+static inline void ipq5332_ppe_reg_write(u32 reg, u32 val)
 {
-	writel(val, (void *)(DEVSOC_PPE_BASE_ADDR + reg));
+	writel(val, (void *)(IPQ5332_PPE_BASE_ADDR + reg));
 }

 void ppe_ipo_rule_reg_set(union ipo_rule_reg_u *hw_reg, int rule_id)
@ -57,7 +57,7 @@ void ppe_ipo_rule_reg_set(union ipo_rule_reg_u *hw_reg, int rule_id)
 	int i;

 	for (i = 0; i < 3; i++) {
-		devsoc_ppe_reg_write(IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS +
+		ipq5332_ppe_reg_write(IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS +
 			(rule_id * IPO_RULE_REG_INC) + (i * 4), hw_reg->val[i]);
 	}
 }
@ -67,7 +67,7 @@ void ppe_ipo_mask_reg_set(union ipo_mask_reg_u *hw_mask, int rule_id)
 	int i;

 	for (i = 0; i < 2; i++) {
-		devsoc_ppe_reg_write((IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS +
+		ipq5332_ppe_reg_write((IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS +
 			(rule_id * IPO_MASK_REG_INC) + (i * 4)), hw_mask->val[i]);
 	}
 }
@ -77,12 +77,12 @@ void ppe_ipo_action_set(union ipo_action_u *hw_act, int rule_id)
 	int i;

 	for (i = 0; i < 5; i++) {
-		devsoc_ppe_reg_write((IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS +
+		ipq5332_ppe_reg_write((IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS +
 			(rule_id * IPO_ACTION_INC) + (i * 4)), hw_act->val[i]);
 	}
 }

-void devsoc_ppe_acl_set(int rule_id, int rule_type, int field0, int field1, int mask, int permit, int deny)
+void ipq5332_ppe_acl_set(int rule_id, int rule_type, int field0, int field1, int mask, int permit, int deny)
 {
 	union ipo_rule_reg_u hw_reg = {0};
 	union ipo_mask_reg_u hw_mask = {0};
@ -135,57 +135,57 @@ void devsoc_ppe_acl_set(int rule_id, int rule_type, int field0, int field1, int
 }

 /*
- * devsoc_ppe_vp_port_tbl_set()
+ * ipq5332_ppe_vp_port_tbl_set()
 */
-static void devsoc_ppe_vp_port_tbl_set(int port, int vsi)
+static void ipq5332_ppe_vp_port_tbl_set(int port, int vsi)
 {
-	u32 addr = DEVSOC_PPE_L3_VP_PORT_TBL_ADDR +
-		 (port * DEVSOC_PPE_L3_VP_PORT_TBL_INC);
-	devsoc_ppe_reg_write(addr, 0x0);
-	devsoc_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10);
-	devsoc_ppe_reg_write(addr + 0x8, 0x0);
-	devsoc_ppe_reg_write(addr + 0xc, 0x0);
+	u32 addr = IPQ5332_PPE_L3_VP_PORT_TBL_ADDR +
+		 (port * IPQ5332_PPE_L3_VP_PORT_TBL_INC);
+	ipq5332_ppe_reg_write(addr, 0x0);
+	ipq5332_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10);
+	ipq5332_ppe_reg_write(addr + 0x8, 0x0);
+	ipq5332_ppe_reg_write(addr + 0xc, 0x0);
 }

 /*
- * devsoc_ppe_ucast_queue_map_tbl_queue_id_set()
+ * ipq5332_ppe_ucast_queue_map_tbl_queue_id_set()
 */
-static void devsoc_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port)
+static void ipq5332_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port)
 {
 	uint32_t val;

-	devsoc_ppe_reg_read(DEVSOC_PPE_QM_UQM_TBL +
-		 (port * DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_INC), &val);
+	ipq5332_ppe_reg_read(IPQ5332_PPE_QM_UQM_TBL +
+		 (port * IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_INC), &val);

 	val |= queue << 4;

-	devsoc_ppe_reg_write(DEVSOC_PPE_QM_UQM_TBL +
-		 (port * DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_INC), val);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_QM_UQM_TBL +
+		 (port * IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_INC), val);
 }

 /*
- * devsoc_vsi_setup()
+ * ipq5332_vsi_setup()
 */
-static void devsoc_vsi_setup(int vsi, uint8_t group_mask)
+static void ipq5332_vsi_setup(int vsi, uint8_t group_mask)
 {
 	uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8
 							    | group_mask);

 	/* Set mask */
-	devsoc_ppe_reg_write(0x063800 + (vsi * 0x10), val);
+	ipq5332_ppe_reg_write(0x063800 + (vsi * 0x10), val);

 	/*  new addr lrn en | station move lrn en */
-	devsoc_ppe_reg_write(0x063804 + (vsi * 0x10), 0x9);
+	ipq5332_ppe_reg_write(0x063804 + (vsi * 0x10), 0x9);
 }

 /*
- * devsoc_gmac_port_disable()
+ * ipq5332_gmac_port_disable()
 */
-static void devsoc_gmac_port_disable(int port)
+static void ipq5332_gmac_port_disable(int port)
 {
-	devsoc_ppe_reg_write(DEVSOC_PPE_MAC_ENABLE + (0x200 * port), 0x70);
-	devsoc_ppe_reg_write(DEVSOC_PPE_MAC_SPEED + (0x200 * port), 0x2);
-	devsoc_ppe_reg_write(DEVSOC_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_ENABLE + (0x200 * port), 0x70);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_SPEED + (0x200 * port), 0x2);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
 }

 /*
@ -197,14 +197,14 @@ void ppe_port_bridge_txmac_set(int port_id, int status)
 {
 	uint32_t reg_value = 0;

-	devsoc_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS +
+	ipq5332_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS +
 		 (port_id * PORT_BRIDGE_CTRL_INC), &reg_value);
 	if (status == 0)
 		reg_value |= TX_MAC_EN;
 	else
 		reg_value &= ~TX_MAC_EN;

-	devsoc_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS +
+	ipq5332_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS +
 		 (port_id * PORT_BRIDGE_CTRL_INC), reg_value);

 }
@ -214,11 +214,11 @@ void ppe_port_txmac_status_set(uint32_t port)
 	uint32_t reg_value = 0;

 	pr_debug("DEBUGGING txmac_status_set......... PORTID = %d\n", port);
-	devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 		 (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), &reg_value);

 	reg_value |=TE;
-	devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 		 (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);

 	pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
@ -231,7 +231,7 @@ void ppe_port_rxmac_status_set(uint32_t port)
 	uint32_t reg_value = 0;

 	pr_debug("DEBUGGING rxmac_status_set......... PORTID = %d\n", port);
-	devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 			MAC_RX_CONFIGURATION_ADDRESS +
 			(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), &reg_value);

@ -239,7 +239,7 @@ void ppe_port_rxmac_status_set(uint32_t port)
 	reg_value |=RE;
 	reg_value |=ACS;
 	reg_value |=CST;
-	devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 			MAC_RX_CONFIGURATION_ADDRESS +
 			(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), reg_value);

@ -252,7 +252,7 @@ void ppe_port_rxmac_status_set(uint32_t port)
 void ppe_mac_packet_filter_set(uint32_t port)
 {
 	pr_debug("DEBUGGING mac_packet_filter_set......... PORTID = %d\n", port);
-	devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 			MAC_PACKET_FILTER_ADDRESS +
 			(port * MAC_PACKET_FILTER_INC), 0x80000081);
 	pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address = 0x%x -> Value = %u\n",
@ -261,11 +261,11 @@ void ppe_mac_packet_filter_set(uint32_t port)
 	      0x80000081);
 }

-#ifndef CONFIG_DEVSOC_RUMI
+#ifndef CONFIG_IPQ5332_RUMI
 /*
- * devsoc_port_mac_clock_reset()
+ * ipq5332_port_mac_clock_reset()
 */
-void devsoc_port_mac_clock_reset(int port)
+void ipq5332_port_mac_clock_reset(int port)
 {
 	int reg_val, reg_val1;

@ -306,7 +306,7 @@ void devsoc_port_mac_clock_reset(int port)
 	mdelay(150);
 }

-void devsoc_speed_clock_set(int port_id, int clk[4])
+void ipq5332_speed_clock_set(int port_id, int clk[4])
 {
 	int i;
 	int reg_val[6];
@ -341,7 +341,7 @@ int phy_status_get_from_ppe(int port_id)
 {
 	uint32_t reg_field = 0;

-	devsoc_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, &reg_field);
+	ipq5332_ppe_reg_read(PORT_PHY_STATUS_ADDRESS, &reg_field);
 	if (port_id == (PORT5 - PPE_UNIPHY_INSTANCE1))
 		reg_field >>= PORT_PHY_STATUS_PORT5_1_OFFSET;
 	else
@ -355,11 +355,11 @@ void ppe_xgmac_10g_r_speed_set(uint32_t port)
 	uint32_t reg_value = 0;

 	pr_debug("DEBUGGING 10g_r_speed_set......... PORTID = %d\n", port);
-	devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 		 (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), &reg_value);

 	reg_value |=JD;
-	devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 		 (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);

 	pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
@ -367,7 +367,7 @@ void ppe_xgmac_10g_r_speed_set(uint32_t port)
 	      reg_value);
 }

-void devsoc_10g_r_speed_set(int port, int status)
+void ipq5332_10g_r_speed_set(int port, int status)
 {
 	ppe_xgmac_10g_r_speed_set(port);
 	ppe_port_bridge_txmac_set(port + 1, status);
@ -382,7 +382,7 @@ void ppe_xgmac_speed_set(uint32_t port, int speed)
 	uint32_t reg_value = 0;

 	pr_debug("\nDEBUGGING xgmac_speed_set......... PORTID = %d\n", port);
-	devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 		 (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), &reg_value);

 	switch(speed) {
@ -406,7 +406,7 @@ void ppe_xgmac_speed_set(uint32_t port, int speed)
 		break;
 	}
 	reg_value |=JD;
-	devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
+	ipq5332_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
 		 (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);
 	pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
 	      PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
@ -414,10 +414,10 @@ void ppe_xgmac_speed_set(uint32_t port, int speed)

 }

-void devsoc_uxsgmii_speed_set(int port, int speed, int duplex,
+void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
 				int status)
 {
-#ifndef CONFIG_DEVSOC_RUMI
+#ifndef CONFIG_IPQ5332_RUMI
 	uint32_t uniphy_index;

 	if (port == PORT0)
@ -429,7 +429,7 @@ void devsoc_uxsgmii_speed_set(int port, int speed, int duplex,
 	ppe_uniphy_usxgmii_speed_set(uniphy_index, speed);
 #endif
 	ppe_xgmac_speed_set(port, speed);
-#ifndef CONFIG_DEVSOC_RUMI
+#ifndef CONFIG_IPQ5332_RUMI
 	ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex);
 	ppe_uniphy_usxgmii_port_reset(uniphy_index);
 #endif
@ -439,163 +439,163 @@ void devsoc_uxsgmii_speed_set(int port, int speed, int duplex,
 	ppe_mac_packet_filter_set(port);
 }

-void devsoc_pqsgmii_speed_set(int port, int speed, int status)
+void ipq5332_pqsgmii_speed_set(int port, int speed, int status)
 {
 	ppe_port_bridge_txmac_set(port + 1, status);
-	devsoc_ppe_reg_write(DEVSOC_PPE_MAC_SPEED + (0x200 * port), speed);
-	devsoc_ppe_reg_write(DEVSOC_PPE_MAC_ENABLE + (0x200 * port), 0x73);
-	devsoc_ppe_reg_write(DEVSOC_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_SPEED + (0x200 * port), speed);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_ENABLE + (0x200 * port), 0x73);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
 }

 /*
- * devsoc_ppe_flow_port_map_tbl_port_num_set()
+ * ipq5332_ppe_flow_port_map_tbl_port_num_set()
 */
-static void devsoc_ppe_flow_port_map_tbl_port_num_set(int queue, int port)
+static void ipq5332_ppe_flow_port_map_tbl_port_num_set(int queue, int port)
 {
-	devsoc_ppe_reg_write(DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL +
-			queue * DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL_INC, port);
-	devsoc_ppe_reg_write(DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL +
-			port * DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL_INC, port);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL +
+			queue * IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_INC, port);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL +
+			port * IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_INC, port);
 }

 /*
- * devsoc_ppe_flow_map_tbl_set()
+ * ipq5332_ppe_flow_map_tbl_set()
 */
-static void devsoc_ppe_flow_map_tbl_set(int queue, int port)
+static void ipq5332_ppe_flow_map_tbl_set(int queue, int port)
 {
 	uint32_t val = port | 0x401000; /* c_drr_wt = 1, e_drr_wt = 1 */
-	devsoc_ppe_reg_write(DEVSOC_PPE_L0_FLOW_MAP_TBL + queue * DEVSOC_PPE_L0_FLOW_MAP_TBL_INC,
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L0_FLOW_MAP_TBL + queue * IPQ5332_PPE_L0_FLOW_MAP_TBL_INC,
 									val);

 	val = port | 0x100400; /* c_drr_wt = 1, e_drr_wt = 1 */
-	devsoc_ppe_reg_write(DEVSOC_PPE_L1_FLOW_MAP_TBL + port * DEVSOC_PPE_L1_FLOW_MAP_TBL_INC,
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L1_FLOW_MAP_TBL + port * IPQ5332_PPE_L1_FLOW_MAP_TBL_INC,
 									val);
 }

 /*
- * devsoc_ppe_tdm_configuration
+ * ipq5332_ppe_tdm_configuration
 */
-static void devsoc_ppe_tdm_configuration(void)
+static void ipq5332_ppe_tdm_configuration(void)
 {
-	devsoc_ppe_reg_write(0xc000, 0x20);
-	devsoc_ppe_reg_write(0xc010, 0x32);
-	devsoc_ppe_reg_write(0xc020, 0x21);
-	devsoc_ppe_reg_write(0xc030, 0x30);
-	devsoc_ppe_reg_write(0xc040, 0x22);
-	devsoc_ppe_reg_write(0xc050, 0x31);
-	devsoc_ppe_reg_write(0xb000, 0x80000006);
+	ipq5332_ppe_reg_write(0xc000, 0x20);
+	ipq5332_ppe_reg_write(0xc010, 0x32);
+	ipq5332_ppe_reg_write(0xc020, 0x21);
+	ipq5332_ppe_reg_write(0xc030, 0x30);
+	ipq5332_ppe_reg_write(0xc040, 0x22);
+	ipq5332_ppe_reg_write(0xc050, 0x31);
+	ipq5332_ppe_reg_write(0xb000, 0x80000006);

-	devsoc_ppe_reg_write(0x47a000, 0xfa10);
-	devsoc_ppe_reg_write(0x47a010, 0xfc21);
-	devsoc_ppe_reg_write(0x47a020, 0xf902);
-	devsoc_ppe_reg_write(0x400000, 0x3);
+	ipq5332_ppe_reg_write(0x47a000, 0xfa10);
+	ipq5332_ppe_reg_write(0x47a010, 0xfc21);
+	ipq5332_ppe_reg_write(0x47a020, 0xf902);
+	ipq5332_ppe_reg_write(0x400000, 0x3);
 }

 /*
- * devsoc_ppe_queue_ac_enable
+ * ipq5332_ppe_queue_ac_enable
 */
-static void devsoc_ppe_queue_ac_enable(void)
+static void ipq5332_ppe_queue_ac_enable(void)
 {
 	int i;

 	/* ucast queue */
 	for (i = 0; i < 256; i++) {
-		devsoc_ppe_reg_write(DEVSOC_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
 					+ (i * 0x10), 0x32120001);
-		devsoc_ppe_reg_write(DEVSOC_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
 					+ (i * 0x10) + 0x4, 0x0);
-		devsoc_ppe_reg_write(DEVSOC_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
 					+ (i * 0x10) + 0x8, 0x0);
-		devsoc_ppe_reg_write(DEVSOC_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR
 					+ (i * 0x10) + 0xc, 0x48000);
 	}

 	/* mcast queue */
 	for (i = 0; i < 44; i++) {
-		devsoc_ppe_reg_write(DEVSOC_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR
 					+ (i * 0x10), 0x00fa0001);
-		devsoc_ppe_reg_write(DEVSOC_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR
 					+ (i * 0x10) + 0x4, 0x0);
-		devsoc_ppe_reg_write(DEVSOC_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR
 					+ (i * 0x10) + 0x8, 0x1200);
 	}
 }

 /*
- * devsoc_ppe_enable_port_counter
+ * ipq5332_ppe_enable_port_counter
 */
-static void devsoc_ppe_enable_port_counter(void)
+static void ipq5332_ppe_enable_port_counter(void)
 {
 	int i;
 	uint32_t reg = 0;

 	for (i = 0; i < 7; i++) {
 		/* MRU_MTU_CTRL_TBL.rx_cnt_en, MRU_MTU_CTRL_TBL.tx_cnt_en */
-		devsoc_ppe_reg_read(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10), &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10), reg);
-		devsoc_ppe_reg_read(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10) + 0x4, &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10) + 0x4, reg | 0x284303);
-		devsoc_ppe_reg_read(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10) + 0x8, &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10) + 0x8, reg);
-		devsoc_ppe_reg_read(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10) + 0xc, &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR
 					+ (i * 0x10) + 0xc, reg);

 		/* MC_MTU_CTRL_TBL.tx_cnt_en */
-		devsoc_ppe_reg_read(DEVSOC_PPE_MC_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_MC_MTU_CTRL_TBL_ADDR
 					+ (i * 0x4), &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_MC_MTU_CTRL_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_MC_MTU_CTRL_TBL_ADDR
 					+ (i * 0x4), reg | 0x10000);

 		/* PORT_EG_VLAN.tx_counting_en */
-		devsoc_ppe_reg_read(DEVSOC_PPE_PORT_EG_VLAN_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_PORT_EG_VLAN_TBL_ADDR
 					+ (i * 0x4), &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_PORT_EG_VLAN_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_EG_VLAN_TBL_ADDR
 					+ (i * 0x4), reg | 0x100);

 		/* TL_PORT_VP_TBL.rx_cnt_en */
-		devsoc_ppe_reg_read(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10), &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10), reg);
-		devsoc_ppe_reg_read(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10) + 0x4, &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10) + 0x4, reg);
-		devsoc_ppe_reg_read(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10) + 0x8, &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10) + 0x8, reg | 0x20000);
-		devsoc_ppe_reg_read(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_read(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10) + 0xc, &reg);
-		devsoc_ppe_reg_write(DEVSOC_PPE_TL_PORT_VP_TBL_ADDR
+		ipq5332_ppe_reg_write(IPQ5332_PPE_TL_PORT_VP_TBL_ADDR
 					+ (i * 0x10) + 0xc, reg);
 	}
 }

 /*
- * devsoc_ppe_c_sp_cfg_tbl_drr_id_set
+ * ipq5332_ppe_c_sp_cfg_tbl_drr_id_set
 */
-static void devsoc_ppe_c_sp_cfg_tbl_drr_id_set(int id)
+static void ipq5332_ppe_c_sp_cfg_tbl_drr_id_set(int id)
 {
-	devsoc_ppe_reg_write(DEVSOC_PPE_L0_C_SP_CFG_TBL + (id * 0x80), id * 2);
-	devsoc_ppe_reg_write(DEVSOC_PPE_L1_C_SP_CFG_TBL + (id * 0x80), id * 2);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L0_C_SP_CFG_TBL + (id * 0x80), id * 2);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L1_C_SP_CFG_TBL + (id * 0x80), id * 2);
 }

 /*
- * devsoc_ppe_e_sp_cfg_tbl_drr_id_set
+ * ipq5332_ppe_e_sp_cfg_tbl_drr_id_set
 */
-static void devsoc_ppe_e_sp_cfg_tbl_drr_id_set(int id)
+static void ipq5332_ppe_e_sp_cfg_tbl_drr_id_set(int id)
 {
-	devsoc_ppe_reg_write(DEVSOC_PPE_L0_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
-	devsoc_ppe_reg_write(DEVSOC_PPE_L1_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L0_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_L1_E_SP_CFG_TBL + (id * 0x80), id * 2 + 1);
 }

 static void ppe_port_mux_set(int port_id, int port_type, int mode)
@ -607,15 +607,15 @@ static void ppe_port_mux_set(int port_id, int port_type, int mode)
 		port_id, port_type, mode);

 	if (port_type == PORT_GMAC_TYPE)
-		mux_mac_type = DEVSOC_PORT_MUX_MAC_TYPE;
+		mux_mac_type = IPQ5332_PORT_MUX_MAC_TYPE;
 	else if (port_type == PORT_XGMAC_TYPE)
-		mux_mac_type = DEVSOC_PORT_MUX_XMAC_TYPE;
+		mux_mac_type = IPQ5332_PORT_MUX_XMAC_TYPE;
 	else
 		printf("\nAttention!!!..Port type configured wrongly..port_id = %d, mode = %d, port_type = %d",
 		       port_id, mode, port_type);

 	port_mux_ctrl.val = 0;
-	devsoc_ppe_reg_read(DEVSOC_PORT_MUX_CTRL, &(port_mux_ctrl.val));
+	ipq5332_ppe_reg_read(IPQ5332_PORT_MUX_CTRL, &(port_mux_ctrl.val));
 	pr_debug("\nBEFORE UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val);


@ -632,7 +632,7 @@ static void ppe_port_mux_set(int port_id, int port_type, int mode)
 			break;
 	}

-	devsoc_ppe_reg_write(DEVSOC_PORT_MUX_CTRL, port_mux_ctrl.val);
+	ipq5332_ppe_reg_write(IPQ5332_PORT_MUX_CTRL, port_mux_ctrl.val);
 	pr_debug("\nAFTER UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val);
 }

@ -660,7 +660,7 @@ void ppe_port_mux_mac_type_set(int port_id, int mode)
 	ppe_port_mux_set(port_id, port_type, mode);
 }

-void devsoc_ppe_interface_mode_init(void)
+void ipq5332_ppe_interface_mode_init(void)
 {
 	uint32_t mode0, mode1;
 	int node;
@ -682,7 +682,7 @@ void devsoc_ppe_interface_mode_init(void)
 		return;
 	}

-#ifndef CONFIG_DEVSOC_RUMI
+#ifndef CONFIG_IPQ5332_RUMI
 	ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0);
 	ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1);
 #endif
@ -695,39 +695,39 @@ void devsoc_ppe_interface_mode_init(void)
 }

 /*
- * devsoc_ppe_provision_init()
+ * ipq5332_ppe_provision_init()
 */
-void devsoc_ppe_provision_init(void)
+void ipq5332_ppe_provision_init(void)
 {
 	int i;
 	uint32_t queue;

 	/* tdm/sched configuration */
-	devsoc_ppe_tdm_configuration();
+	ipq5332_ppe_tdm_configuration();

-#ifdef CONFIG_DEVSOC_BRIDGED_MODE
+#ifdef CONFIG_IPQ5332_BRIDGED_MODE
 	/* Add CPU port 0 to VSI 2 */
-	devsoc_ppe_vp_port_tbl_set(0, 2);
+	ipq5332_ppe_vp_port_tbl_set(0, 2);

 	/* Add port 1 - 4 to VSI 2 */
-	devsoc_ppe_vp_port_tbl_set(1, 2);
-	devsoc_ppe_vp_port_tbl_set(2, 2);
-	devsoc_ppe_vp_port_tbl_set(3, 2);
-	devsoc_ppe_vp_port_tbl_set(4, 2);
-	devsoc_ppe_vp_port_tbl_set(5, 2);
-	devsoc_ppe_vp_port_tbl_set(6, 2);
+	ipq5332_ppe_vp_port_tbl_set(1, 2);
+	ipq5332_ppe_vp_port_tbl_set(2, 2);
+	ipq5332_ppe_vp_port_tbl_set(3, 2);
+	ipq5332_ppe_vp_port_tbl_set(4, 2);
+	ipq5332_ppe_vp_port_tbl_set(5, 2);
+	ipq5332_ppe_vp_port_tbl_set(6, 2);

 #else
-	devsoc_ppe_vp_port_tbl_set(1, 2);
-	devsoc_ppe_vp_port_tbl_set(2, 3);
-	devsoc_ppe_vp_port_tbl_set(3, 4);
-	devsoc_ppe_vp_port_tbl_set(4, 5);
-	devsoc_ppe_vp_port_tbl_set(5, 6);
-	devsoc_ppe_vp_port_tbl_set(6, 7);
+	ipq5332_ppe_vp_port_tbl_set(1, 2);
+	ipq5332_ppe_vp_port_tbl_set(2, 3);
+	ipq5332_ppe_vp_port_tbl_set(3, 4);
+	ipq5332_ppe_vp_port_tbl_set(4, 5);
+	ipq5332_ppe_vp_port_tbl_set(5, 6);
+	ipq5332_ppe_vp_port_tbl_set(6, 7);
 #endif

 	/* Unicast priority map */
-	devsoc_ppe_reg_write(DEVSOC_PPE_QM_UPM_TBL, 0);
+	ipq5332_ppe_reg_write(IPQ5332_PPE_QM_UPM_TBL, 0);

 	/* Port0 - 7 unicast queue settings */
 	for (i = 0; i < 8; i++) {
@ -736,37 +736,37 @@ void devsoc_ppe_provision_init(void)
 		else
 			queue = ((i * 0x10) + 0x70);

-		devsoc_ppe_ucast_queue_map_tbl_queue_id_set(queue, i);
-		devsoc_ppe_flow_port_map_tbl_port_num_set(queue, i);
-		devsoc_ppe_flow_map_tbl_set(queue, i);
-		devsoc_ppe_c_sp_cfg_tbl_drr_id_set(i);
-		devsoc_ppe_e_sp_cfg_tbl_drr_id_set(i);
+		ipq5332_ppe_ucast_queue_map_tbl_queue_id_set(queue, i);
+		ipq5332_ppe_flow_port_map_tbl_port_num_set(queue, i);
+		ipq5332_ppe_flow_map_tbl_set(queue, i);
+		ipq5332_ppe_c_sp_cfg_tbl_drr_id_set(i);
+		ipq5332_ppe_e_sp_cfg_tbl_drr_id_set(i);
 	}

 	/* Port0 multicast queue */
-	devsoc_ppe_reg_write(0x409000, 0x00000000);
-	devsoc_ppe_reg_write(0x403000, 0x00401000);
+	ipq5332_ppe_reg_write(0x409000, 0x00000000);
+	ipq5332_ppe_reg_write(0x403000, 0x00401000);

 	/* Port1 - 7 multicast queue */
 	for (i = 1; i < 8; i++) {
-		devsoc_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i);
-		devsoc_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i);
+		ipq5332_ppe_reg_write(0x409100 + ((i - 1) * 0x40), i);
+		ipq5332_ppe_reg_write(0x403100 + ((i - 1) * 0x40), 0x401000 | i);
 	}

 	/* ac enable for queues - disable queue tail drop */
-	devsoc_ppe_queue_ac_enable();
+	ipq5332_ppe_queue_ac_enable();

 	/* enable queue counter */
-	devsoc_ppe_reg_write(0x020044,0x4);
+	ipq5332_ppe_reg_write(0x020044,0x4);

 	/* assign the ac group 0 with buffer number */
-	devsoc_ppe_reg_write(0x84c000, 0x0);
-	devsoc_ppe_reg_write(0x84c004, 0x7D00);
-	devsoc_ppe_reg_write(0x84c008, 0x0);
-	devsoc_ppe_reg_write(0x84c00c, 0x0);
+	ipq5332_ppe_reg_write(0x84c000, 0x0);
+	ipq5332_ppe_reg_write(0x84c004, 0x7D00);
+	ipq5332_ppe_reg_write(0x84c008, 0x0);
+	ipq5332_ppe_reg_write(0x84c00c, 0x0);

 	/* enable physical/virtual port TX/RX counters for all ports (0-6) */
-	devsoc_ppe_enable_port_counter();
+	ipq5332_ppe_enable_port_counter();

 	/*
 	 * Port0 - TX_EN is set by default, Port1 - LRN_EN is set
@ -776,52 +776,52 @@ void devsoc_ppe_provision_init(void)
 	 */
 	for (i = 0; i < 8; i++) {
 		if (i == 0)
-			devsoc_ppe_reg_write(DEVSOC_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_TXMAC_EN |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
+			ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_TXMAC_EN |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
 		else if (i == 7)
-			devsoc_ppe_reg_write(DEVSOC_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
+			ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN);
 		else
-			devsoc_ppe_reg_write(DEVSOC_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
-			      DEVSOC_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP);
+			ipq5332_ppe_reg_write(IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET + (i * 4),
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN |
+			      IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP);
 	}

 	/* Global learning */
-	devsoc_ppe_reg_write(0x060038, 0xc0);
+	ipq5332_ppe_reg_write(0x060038, 0xc0);

-#ifdef CONFIG_DEVSOC_BRIDGED_MODE
-	devsoc_vsi_setup(2, 0x7f);
+#ifdef CONFIG_IPQ5332_BRIDGED_MODE
+	ipq5332_vsi_setup(2, 0x7f);
 #else
-	devsoc_vsi_setup(2, 0x03);
-	devsoc_vsi_setup(3, 0x05);
-	devsoc_vsi_setup(4, 0x09);
-	devsoc_vsi_setup(5, 0x11);
-	devsoc_vsi_setup(6, 0x21);
-	devsoc_vsi_setup(7, 0x41);
+	ipq5332_vsi_setup(2, 0x03);
+	ipq5332_vsi_setup(3, 0x05);
+	ipq5332_vsi_setup(4, 0x09);
+	ipq5332_vsi_setup(5, 0x11);
+	ipq5332_vsi_setup(6, 0x21);
+	ipq5332_vsi_setup(7, 0x41);
 #endif

 	/* Port 0-7 STP */
 	for (i = 0; i < 8; i++)
-		devsoc_ppe_reg_write(DEVSOC_PPE_STP_BASE + (0x4 * i), 0x3);
+		ipq5332_ppe_reg_write(IPQ5332_PPE_STP_BASE + (0x4 * i), 0x3);

-	devsoc_ppe_interface_mode_init();
+	ipq5332_ppe_interface_mode_init();
 	/* Port 1-2 disable */
 	for (i = 0; i < 2; i++) {
-		devsoc_gmac_port_disable(i);
+		ipq5332_gmac_port_disable(i);
 		ppe_port_bridge_txmac_set(i + 1, 1);
 	}

 	/* Allowing DHCP packets */
-	devsoc_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67, 0xffff, 0, 0);
-	devsoc_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68, 0xffff, 0, 0);
+	ipq5332_ppe_acl_set(0, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 67, 0xffff, 0, 0);
+	ipq5332_ppe_acl_set(1, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 68, 0xffff, 0, 0);
 	/* Dropping all the UDP packets */
-	devsoc_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0, 1);
+	ipq5332_ppe_acl_set(2, ADPT_ACL_HPPE_IPV4_DIP_RULE, UDP_PKT, 0, 0, 0, 1);
 }
--- a/drivers/net/ipq5332/ipq5332_ppe.h
+++ b/drivers/net/ipq5332/ipq5332_ppe.h
@ -26,16 +26,16 @@
 #include <phy.h>
 #include <miiphy.h>

-#define DEVSOC_PPE_BASE_ADDR			0x3a000000
+#define IPQ5332_PPE_BASE_ADDR			0x3a000000

-#define DEVSOC_PORT5_MUX_PCS_UNIPHY0		0x0
-#define DEVSOC_PORT5_MUX_PCS_UNIPHY1		0x1
+#define IPQ5332_PORT5_MUX_PCS_UNIPHY0		0x0
+#define IPQ5332_PORT5_MUX_PCS_UNIPHY1		0x1

 #define PORT_GMAC_TYPE				1
 #define PORT_XGMAC_TYPE				2

-#define DEVSOC_PORT_MUX_MAC_TYPE		0
-#define DEVSOC_PORT_MUX_XMAC_TYPE		1
+#define IPQ5332_PORT_MUX_MAC_TYPE		0
+#define IPQ5332_PORT_MUX_XMAC_TYPE		1

 struct port_mux_ctrl {
 	uint32_t port1_pcs_sel:1;
@ -110,121 +110,121 @@ union ipo_action_u {
        struct ipo_action bf;
 };

-#define DEVSOC_PORT_MUX_CTRL			0x10
-#define DEVSOC_PORT_MUX_CTRL_NUM		1
-#define DEVSOC_PORT_MUX_CTRL_INC		0x4
-#define DEVSOC_PORT_MUX_CTRL_DEFAULT		0x0
+#define IPQ5332_PORT_MUX_CTRL			0x10
+#define IPQ5332_PORT_MUX_CTRL_NUM		1
+#define IPQ5332_PORT_MUX_CTRL_INC		0x4
+#define IPQ5332_PORT_MUX_CTRL_DEFAULT		0x0

 #define PORT_PHY_STATUS_ADDRESS			0x44
 #define PORT_PHY_STATUS_PORT5_1_OFFSET		8
 #define PORT_PHY_STATUS_PORT6_OFFSET		16

-#define DEVSOC_PPE_IPE_L3_BASE_ADDR		0x200000
-#define DEVSOC_PPE_L3_VP_PORT_TBL_ADDR		(DEVSOC_PPE_IPE_L3_BASE_ADDR + 0x4000)
-#define DEVSOC_PPE_L3_VP_PORT_TBL_INC		0x10
+#define IPQ5332_PPE_IPE_L3_BASE_ADDR		0x200000
+#define IPQ5332_PPE_L3_VP_PORT_TBL_ADDR		(IPQ5332_PPE_IPE_L3_BASE_ADDR + 0x4000)
+#define IPQ5332_PPE_L3_VP_PORT_TBL_INC		0x10

-#define DEVSOC_PPE_TL_PORT_VP_TBL_ADDR		0x302000
-#define DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR	0x65000
-#define DEVSOC_PPE_MC_MTU_CTRL_TBL_ADDR	0x60a00
-#define DEVSOC_PPE_PORT_EG_VLAN_TBL_ADDR	0x20020
+#define IPQ5332_PPE_TL_PORT_VP_TBL_ADDR		0x302000
+#define IPQ5332_PPE_MRU_MTU_CTRL_TBL_ADDR	0x65000
+#define IPQ5332_PPE_MC_MTU_CTRL_TBL_ADDR	0x60a00
+#define IPQ5332_PPE_PORT_EG_VLAN_TBL_ADDR	0x20020

-#define DEVSOC_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR 0x848000
-#define DEVSOC_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR 0x84a000
-#define DEVSOC_PPE_QUEUE_MANAGER_BASE_ADDR	0x800000
-#define DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_ADDR	0x10000
-#define DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_INC	0x10
-#define DEVSOC_PPE_QM_UQM_TBL			(DEVSOC_PPE_QUEUE_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_ADDR)
-#define DEVSOC_PPE_UCAST_PRIORITY_MAP_TBL_ADDR	0x42000
-#define DEVSOC_PPE_QM_UPM_TBL			(DEVSOC_PPE_QUEUE_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_UCAST_PRIORITY_MAP_TBL_ADDR)
+#define IPQ5332_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR 0x848000
+#define IPQ5332_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR 0x84a000
+#define IPQ5332_PPE_QUEUE_MANAGER_BASE_ADDR	0x800000
+#define IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_ADDR	0x10000
+#define IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_INC	0x10
+#define IPQ5332_PPE_QM_UQM_TBL			(IPQ5332_PPE_QUEUE_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_UCAST_QUEUE_MAP_TBL_ADDR)
+#define IPQ5332_PPE_UCAST_PRIORITY_MAP_TBL_ADDR	0x42000
+#define IPQ5332_PPE_QM_UPM_TBL			(IPQ5332_PPE_QUEUE_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_UCAST_PRIORITY_MAP_TBL_ADDR)

-#define DEVSOC_PPE_STP_BASE			0x060100
-#define DEVSOC_PPE_MAC_ENABLE			0x001000
-#define DEVSOC_PPE_MAC_SPEED			0x001004
-#define DEVSOC_PPE_MAC_MIB_CTL			0x001034
+#define IPQ5332_PPE_STP_BASE			0x060100
+#define IPQ5332_PPE_MAC_ENABLE			0x001000
+#define IPQ5332_PPE_MAC_SPEED			0x001004
+#define IPQ5332_PPE_MAC_MIB_CTL			0x001034

-#define DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR	0x400000
-#define DEVSOC_PPE_TM_SHP_CFG_L0_OFFSET	0x00000030
-#define DEVSOC_PPE_TM_SHP_CFG_L1_OFFSET	0x00000034
-#define DEVSOC_PPE_TM_SHP_CFG_L0		DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-						DEVSOC_PPE_TM_SHP_CFG_L0_OFFSET
-#define DEVSOC_PPE_TM_SHP_CFG_L1		DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-						DEVSOC_PPE_TM_SHP_CFG_L1_OFFSET
+#define IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR	0x400000
+#define IPQ5332_PPE_TM_SHP_CFG_L0_OFFSET	0x00000030
+#define IPQ5332_PPE_TM_SHP_CFG_L1_OFFSET	0x00000034
+#define IPQ5332_PPE_TM_SHP_CFG_L0		IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+						IPQ5332_PPE_TM_SHP_CFG_L0_OFFSET
+#define IPQ5332_PPE_TM_SHP_CFG_L1		IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+						IPQ5332_PPE_TM_SHP_CFG_L1_OFFSET

-#define DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL_ADDR	0x10000
-#define DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL_INC	0x10
-#define DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL	(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL_ADDR)
+#define IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_ADDR	0x10000
+#define IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_INC	0x10
+#define IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL	(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L0_FLOW_PORT_MAP_TBL_ADDR)

-#define DEVSOC_PPE_L0_FLOW_MAP_TBL_ADDR	0x2000
-#define DEVSOC_PPE_L0_FLOW_MAP_TBL_INC		0x10
-#define DEVSOC_PPE_L0_FLOW_MAP_TBL		(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L0_FLOW_MAP_TBL_ADDR)
+#define IPQ5332_PPE_L0_FLOW_MAP_TBL_ADDR	0x2000
+#define IPQ5332_PPE_L0_FLOW_MAP_TBL_INC		0x10
+#define IPQ5332_PPE_L0_FLOW_MAP_TBL		(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L0_FLOW_MAP_TBL_ADDR)

-#define DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL_ADDR	0x46000
-#define DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL_INC	0x10
-#define DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL	(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL_ADDR)
+#define IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_ADDR	0x46000
+#define IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_INC	0x10
+#define IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL	(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L1_FLOW_PORT_MAP_TBL_ADDR)

-#define DEVSOC_PPE_L1_FLOW_MAP_TBL_ADDR	0x40000
-#define DEVSOC_PPE_L1_FLOW_MAP_TBL_INC		0x10
-#define DEVSOC_PPE_L1_FLOW_MAP_TBL		(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L1_FLOW_MAP_TBL_ADDR)
+#define IPQ5332_PPE_L1_FLOW_MAP_TBL_ADDR	0x40000
+#define IPQ5332_PPE_L1_FLOW_MAP_TBL_INC		0x10
+#define IPQ5332_PPE_L1_FLOW_MAP_TBL		(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L1_FLOW_MAP_TBL_ADDR)

-#define DEVSOC_PPE_L0_C_SP_CFG_TBL_ADDR	0x4000
-#define DEVSOC_PPE_L0_C_SP_CFG_TBL		(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L0_C_SP_CFG_TBL_ADDR)
+#define IPQ5332_PPE_L0_C_SP_CFG_TBL_ADDR	0x4000
+#define IPQ5332_PPE_L0_C_SP_CFG_TBL		(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L0_C_SP_CFG_TBL_ADDR)

-#define DEVSOC_PPE_L1_C_SP_CFG_TBL_ADDR	0x42000
-#define DEVSOC_PPE_L1_C_SP_CFG_TBL		(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L1_C_SP_CFG_TBL_ADDR)
+#define IPQ5332_PPE_L1_C_SP_CFG_TBL_ADDR	0x42000
+#define IPQ5332_PPE_L1_C_SP_CFG_TBL		(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L1_C_SP_CFG_TBL_ADDR)

-#define DEVSOC_PPE_L0_E_SP_CFG_TBL_ADDR	0x6000
-#define DEVSOC_PPE_L0_E_SP_CFG_TBL		(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L0_E_SP_CFG_TBL_ADDR)
+#define IPQ5332_PPE_L0_E_SP_CFG_TBL_ADDR	0x6000
+#define IPQ5332_PPE_L0_E_SP_CFG_TBL		(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L0_E_SP_CFG_TBL_ADDR)

-#define DEVSOC_PPE_L1_E_SP_CFG_TBL_ADDR		0x44000
-#define DEVSOC_PPE_L1_E_SP_CFG_TBL		(DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
-					 DEVSOC_PPE_L1_E_SP_CFG_TBL_ADDR)
+#define IPQ5332_PPE_L1_E_SP_CFG_TBL_ADDR		0x44000
+#define IPQ5332_PPE_L1_E_SP_CFG_TBL		(IPQ5332_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
+					 IPQ5332_PPE_L1_E_SP_CFG_TBL_ADDR)

-#define DEVSOC_PPE_FPGA_GPIO_BASE_ADDR		0x01008000
+#define IPQ5332_PPE_FPGA_GPIO_BASE_ADDR		0x01008000

-#define DEVSOC_PPE_MAC_PORT_MUX_OFFSET		0x10
-#define DEVSOC_PPE_FPGA_GPIO_OFFSET		0xc000
-#define DEVSOC_PPE_FPGA_SCHED_OFFSET		0x47a000
-#define DEVSOC_PPE_TDM_CFG_DEPTH_OFFSET	0xb000
-#define DEVSOC_PPE_TDM_SCHED_DEPTH_OFFSET	0x400000
-#define DEVSOC_PPE_PORT_BRIDGE_CTRL_OFFSET	0x060300
+#define IPQ5332_PPE_MAC_PORT_MUX_OFFSET		0x10
+#define IPQ5332_PPE_FPGA_GPIO_OFFSET		0xc000
+#define IPQ5332_PPE_FPGA_SCHED_OFFSET		0x47a000
+#define IPQ5332_PPE_TDM_CFG_DEPTH_OFFSET	0xb000
+#define IPQ5332_PPE_TDM_SCHED_DEPTH_OFFSET	0x400000
+#define IPQ5332_PPE_PORT_BRIDGE_CTRL_OFFSET	0x060300

-#define DEVSOC_PPE_TDM_CFG_DEPTH_VAL		0x80000064
-#define DEVSOC_PPE_MAC_PORT_MUX_OFFSET_VAL	0x15
-#define DEVSOC_PPE_TDM_SCHED_DEPTH_VAL		0x32
-#define DEVSOC_PPE_TDM_CFG_VALID		0x20
-#define DEVSOC_PPE_TDM_CFG_DIR_INGRESS		0x0
-#define DEVSOC_PPE_TDM_CFG_DIR_EGRESS		0x10
-#define DEVSOC_PPE_PORT_EDMA			0x0
-#define DEVSOC_PPE_PORT_QTI1			0x1
-#define DEVSOC_PPE_PORT_QTI2			0x2
-#define DEVSOC_PPE_PORT_QTI3			0x3
-#define DEVSOC_PPE_PORT_QTI4			0x4
-#define DEVSOC_PPE_PORT_XGMAC1			0x5
-#define DEVSOC_PPE_PORT_XGMAC2			0x6
-#define DEVSOC_PPE_PORT_CRYPTO1		0x7
-#define DEVSOC_PPE_PORT_BRIDGE_CTRL_PROMISC_EN	0x20000
-#define DEVSOC_PPE_PORT_BRIDGE_CTRL_TXMAC_EN	0x10000
-#define DEVSOC_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP	0x7f00
-#define DEVSOC_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN	0x8
-#define DEVSOC_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN	0x1
+#define IPQ5332_PPE_TDM_CFG_DEPTH_VAL		0x80000064
+#define IPQ5332_PPE_MAC_PORT_MUX_OFFSET_VAL	0x15
+#define IPQ5332_PPE_TDM_SCHED_DEPTH_VAL		0x32
+#define IPQ5332_PPE_TDM_CFG_VALID		0x20
+#define IPQ5332_PPE_TDM_CFG_DIR_INGRESS		0x0
+#define IPQ5332_PPE_TDM_CFG_DIR_EGRESS		0x10
+#define IPQ5332_PPE_PORT_EDMA			0x0
+#define IPQ5332_PPE_PORT_QTI1			0x1
+#define IPQ5332_PPE_PORT_QTI2			0x2
+#define IPQ5332_PPE_PORT_QTI3			0x3
+#define IPQ5332_PPE_PORT_QTI4			0x4
+#define IPQ5332_PPE_PORT_XGMAC1			0x5
+#define IPQ5332_PPE_PORT_XGMAC2			0x6
+#define IPQ5332_PPE_PORT_CRYPTO1		0x7
+#define IPQ5332_PPE_PORT_BRIDGE_CTRL_PROMISC_EN	0x20000
+#define IPQ5332_PPE_PORT_BRIDGE_CTRL_TXMAC_EN	0x10000
+#define IPQ5332_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP	0x7f00
+#define IPQ5332_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN	0x8
+#define IPQ5332_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN	0x1

-#define DEVSOC_PPE_PORT_EDMA_BITPOS		0x1
-#define DEVSOC_PPE_PORT_QTI1_BITPOS		(1 << DEVSOC_PPE_PORT_QTI1)
-#define DEVSOC_PPE_PORT_QTI2_BITPOS		(1 << DEVSOC_PPE_PORT_QTI2)
-#define DEVSOC_PPE_PORT_QTI3_BITPOS		(1 << DEVSOC_PPE_PORT_QTI3)
-#define DEVSOC_PPE_PORT_QTI4_BITPOS		(1 << DEVSOC_PPE_PORT_QTI4)
-#define DEVSOC_PPE_PORT_XGMAC1_BITPOS		(1 << DEVSOC_PPE_PORT_XGMAC1)
-#define DEVSOC_PPE_PORT_XGMAC2_BITPOS		(1 << DEVSOC_PPE_PORT_XGMAC2)
-#define DEVSOC_PPE_PORT_CRYPTO1_BITPOS		(1 << DEVSOC_PPE_PORT_CRYPTO1)
+#define IPQ5332_PPE_PORT_EDMA_BITPOS		0x1
+#define IPQ5332_PPE_PORT_QTI1_BITPOS		(1 << IPQ5332_PPE_PORT_QTI1)
+#define IPQ5332_PPE_PORT_QTI2_BITPOS		(1 << IPQ5332_PPE_PORT_QTI2)
+#define IPQ5332_PPE_PORT_QTI3_BITPOS		(1 << IPQ5332_PPE_PORT_QTI3)
+#define IPQ5332_PPE_PORT_QTI4_BITPOS		(1 << IPQ5332_PPE_PORT_QTI4)
+#define IPQ5332_PPE_PORT_XGMAC1_BITPOS		(1 << IPQ5332_PPE_PORT_XGMAC1)
+#define IPQ5332_PPE_PORT_XGMAC2_BITPOS		(1 << IPQ5332_PPE_PORT_XGMAC2)
+#define IPQ5332_PPE_PORT_CRYPTO1_BITPOS		(1 << IPQ5332_PPE_PORT_CRYPTO1)

 #define PPE_SWITCH_NSS_SWITCH_XGMAC0		0x500000
 #define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION	0x4000
--- a/drivers/net/ipq5332/ipq5332_uniphy.c
+++ b/drivers/net/ipq5332/ipq5332_uniphy.c
@ -22,10 +22,10 @@
 #include <phy.h>
 #include <net.h>
 #include <miiphy.h>
-#include <asm/arch-devsoc/edma_regs.h>
-#include "devsoc_edma.h"
-#include "devsoc_uniphy.h"
-#include "devsoc_ppe.h"
+#include <asm/arch-ipq5332/edma_regs.h>
+#include "ipq5332_edma.h"
+#include "ipq5332_uniphy.h"
+#include "ipq5332_ppe.h"
 #include <fdtdec.h>
 #include "ipq_phy.h"

@ -35,7 +35,7 @@ extern int ipq_mdio_write(int mii_id,
 		int regnum, u16 value);
 extern int ipq_mdio_read(int mii_id,
 		int regnum, ushort *data);
-extern void devsoc_qca8075_phy_serdes_reset(u32 phy_id);
+extern void ipq5332_qca8075_phy_serdes_reset(u32 phy_id);

 void csr1_write(int phy_id, int addr, int  value)
 {
@ -175,8 +175,8 @@ static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index)
 	}
 	mdelay(100);
 	ppe_uniphy_calibration(uniphy_index);
-#ifdef CONFIG_DEVSOC_QCA8075_PHY
-	devsoc_qca8075_phy_serdes_reset(0x10);
+#ifdef CONFIG_IPQ5332_QCA8075_PHY
+	ipq5332_qca8075_phy_serdes_reset(0x10);
 #endif
 }

--- a/drivers/net/ipq_common/ipq_aquantia_phy.c
+++ b/drivers/net/ipq_common/ipq_aquantia_phy.c
@ -59,7 +59,7 @@ extern int ipq_mdio_read(int mii_id,
 		int regnum, ushort *data);

 extern int ipq_sw_mdio_init(const char *);
-extern void devsoc_eth_initialize(void);
+extern void ipq5332_eth_initialize(void);
 static int program_ethphy_fw(unsigned int phy_addr,
 			 uint32_t load_addr,uint32_t file_size );
 static qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
@ -578,7 +578,7 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		phy_addr = simple_strtoul(argv[1], NULL, 16);

 	miiphy_init();
-	devsoc_eth_initialize();
+	ipq5332_eth_initialize();
 	ipq_sw_mdio_init("IPQ MDIO0");
 	ipq_board_fw_download(phy_addr);
 	return 0;
--- a/drivers/net/ipq_common/ipq_phy.h
+++ b/drivers/net/ipq_common/ipq_phy.h
@ -23,7 +23,7 @@
 #define PHY_MAX		6
 #define IPQ9574_PHY_MAX	6
 #define IPQ6018_PHY_MAX 5
-#define DEVSOC_PHY_MAX	2
+#define IPQ5332_PHY_MAX	2

 #define QCA8084_MAX_PORTS	6

--- a/drivers/pci/pci_ipq.c
+++ b/drivers/pci/pci_ipq.c
@ -1006,7 +1006,7 @@ static const struct udevice_id pcie_ver_ids[] = {
 	{ .compatible = "qcom,ipq807x-pcie", .data = PCIE_V2 },
 	{ .compatible = "qcom,ipq6018-pcie", .data = PCIE_V2 },
 	{ .compatible = "qcom,ipq5018-pcie", .data = PCIE_V2 },
-	{ .compatible = "qcom,devsoc-pcie", .data = PCIE_V2 },
+	{ .compatible = "qcom,ipq5332-pcie", .data = PCIE_V2 },
 	{ .compatible = "qcom,ipq9574-pcie", .data = PCIE_V2 },
 	{ },
 };
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@ -12,7 +12,7 @@ obj-$(CONFIG_ARCH_IPQ807x) += qca_uart.o
 obj-$(CONFIG_ARCH_IPQ806x) += qca_uart.o
 obj-$(CONFIG_ARCH_IPQ40xx) += qca_uart.o
 obj-$(CONFIG_ARCH_IPQ5018) += qca_uart.o
-obj-$(CONFIG_ARCH_DEVSOC) += qca_uart.o
+obj-$(CONFIG_ARCH_IPQ5332) += qca_uart.o
 obj-$(CONFIG_ARCH_IPQ6018) += qca_uart.o
 obj-$(CONFIG_ARCH_IPQ9574) += qca_uart.o
 ifdef CONFIG_DM_SERIAL
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@ -37,7 +37,7 @@ obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi_bam.o
 obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi_bam.o
 obj-$(CONFIG_ARCH_IPQ6018) += qca_qup_spi_bam.o
 obj-$(CONFIG_ARCH_IPQ5018) += qca_qup_spi_bam.o
-obj-$(CONFIG_ARCH_DEVSOC) += qca_qup_spi_bam.o
+obj-$(CONFIG_ARCH_IPQ5332) += qca_qup_spi_bam.o
 obj-$(CONFIG_ARCH_IPQ9574) += qca_qup_spi_bam.o

 obj-$(CONFIG_ARCH_IPQ806x) += ipq_spi.o
--- a/include/common.h
+++ b/include/common.h
@ -38,8 +38,8 @@ typedef volatile unsigned char	vu_char;
 #elif defined(CONFIG_IPQ5018)
 #include <../board/qca/arm/ipq5018/ipq5018.h>

-#elif defined(CONFIG_DEVSOC)
-#include <../board/qca/arm/devsoc/devsoc.h>
+#elif defined(CONFIG_IPQ5332)
+#include <../board/qca/arm/ipq5332/ipq5332.h>

 #elif defined(CONFIG_IPQ6018)
 #include <../board/qca/arm/ipq6018/ipq6018.h>
@ -421,7 +421,7 @@ ulong getenv_hex(const char *varname, ulong default_val);
 int getenv_yesno(const char *var);
 #if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) ||	\
 	defined(CONFIG_IPQ806X_ENV) || defined(CONFIG_IPQ5018_ENV) ||	\
-	defined(CONFIG_DEVSOC_ENV) || defined(CONFIG_IPQ6018_ENV) ||	\
+	defined(CONFIG_IPQ5332_ENV) || defined(CONFIG_IPQ6018_ENV) ||	\
 	defined(CONFIG_IPQ9574_ENV)
 extern int (*saveenv)(void);
 #else
--- a/include/configs/ipq5332.h
+++ b/include/configs/ipq5332.h
@ -13,15 +13,15 @@
 * GNU General Public License for more details.
 */

-#ifndef _DEVSOC_H
-#define _DEVSOC_H
+#ifndef _IPQ5332_H
+#define _IPQ5332_H

 #ifndef DO_DEPS_ONLY
 #include <generated/asm-offsets.h>
 #endif

-#define CONFIG_DEVSOC
-#define CONFIG_DEVSOC_RUMI
+#define CONFIG_IPQ5332
+#define CONFIG_IPQ5332_RUMI
 #undef	CONFIG_QCA_DISABLE_SCM
 #define CONFIG_SPI_FLASH_CYPRESS
 #define CONFIG_SYS_NO_FLASH
@ -40,7 +40,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT

-#define CONFIG_DEVSOC_UART
+#define CONFIG_IPQ5332_UART
 #define CONFIG_NR_DRAM_BANKS			1
 #define CONFIG_SKIP_LOWLEVEL_INIT

@ -154,7 +154,7 @@ extern loff_t board_env_range;
 extern loff_t board_env_size;
 #endif

-#define CONFIG_DEVSOC_ENV			1
+#define CONFIG_IPQ5332_ENV			1
 #define CONFIG_ENV_OFFSET			board_env_offset
 #define CONFIG_ENV_SIZE				CONFIG_ENV_SIZE_MAX
 #define CONFIG_ENV_RANGE			board_env_range
@ -228,9 +228,9 @@ extern loff_t board_env_size;
 /*
 * Ethernet Configs
 */
-#define CONFIG_DEVSOC_EDMA
-#ifdef CONFIG_DEVSOC_EDMA
-#define CONFIG_DEVSOC_BRIDGED_MODE	1
+#define CONFIG_IPQ5332_EDMA
+#ifdef CONFIG_IPQ5332_EDMA
+#define CONFIG_IPQ5332_BRIDGED_MODE	1
 #define CONFIG_NET_RETRY_COUNT		5
 #define CONFIG_SYS_RX_ETH_BUFFER	128
 #define CONFIG_TFTP_BLOCKSIZE		1280
@ -439,4 +439,4 @@ extern loff_t board_env_size;
 #undef CONFIG_BOOTM_RTEMS
 #undef CONFIG_BOOTM_VXWORKS

-#endif /* _DEVSOC_H */
+#endif /* _IPQ5332_H */
--- a/include/dt-bindings/qcom/eth-ipq5332.h
+++ b/include/dt-bindings/qcom/eth-ipq5332.h
@ -13,8 +13,8 @@
 * GNU General Public License for more details.
 */

-#ifndef __DT_BINDINGS_DEVSOC_ETH_H__
-#define __DT_BINDINGS_DEVSOC_ETH_H__
+#ifndef __DT_BINDINGS_IPQ5332_ETH_H__
+#define __DT_BINDINGS_IPQ5332_ETH_H__

 /* ESS Switch Mac Modes */
 #define PORT_WRAPPER_PSGMII		0
--- a/include/dt-bindings/qcom/gpio-ipq5332.h
+++ b/include/dt-bindings/qcom/gpio-ipq5332.h
@ -13,8 +13,8 @@
 * GNU General Public License for more details.
 */

-#ifndef __DT_BINDINGS_DEVSOC_GPIO_H__
-#define __DT_BINDINGS_DEVSOC_GPIO_H__
+#ifndef __DT_BINDINGS_IPQ5332_GPIO_H__
+#define __DT_BINDINGS_IPQ5332_GPIO_H__

 /* GPIO TLMM: Direction */
 #define GPIO_INPUT              0