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drivers: net: add MDIO clause 45 support
Change-Id: Iba47a99967bed745083097a11a767062b26d21e3 Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy
Gerrit - the friendly Code Review server
parent
0012c3f879
commit
1a4b370d2e
2 changed files with 229 additions and 6 deletions
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@ -5,6 +5,8 @@
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* (C) Copyright 2001
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* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
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*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -20,6 +22,17 @@
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#define BB_MII_RELOCATE(v,off) (v += (v?off:0))
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#define MDIO_READ 2
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#define MDIO_WRITE 1
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#define MDIO_C45 (1<<15)
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#define MDIO_C45_ADDR (MDIO_C45 | 0)
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#define MDIO_C45_READ (MDIO_C45 | 3)
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#define MDIO_C45_WRITE (MDIO_C45 | 1)
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#define MDIO_SETUP_TIME 10
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#define MDIO_HOLD_TIME 10
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_BITBANGMII_MULTI
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@ -150,8 +163,8 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
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* Utility to send the preamble, address, and register (common to read
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* and write).
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*/
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static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
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unsigned char addr, unsigned char reg)
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static void miiphy_pre(struct bb_miiphy_bus *bus, int read,
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unsigned int addr, unsigned int reg)
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{
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int j;
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@ -172,24 +185,35 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
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bus->delay(bus);
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}
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/* send the start bit (01) and the read opcode (10) or write (10) */
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/* send the start bit (01) and the read opcode (10) or write (10)
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* Clause 45 operation uses 00 for the start and 11, 10 for read/write
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*/
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 1);
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if (read & MDIO_C45)
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bus->set_mdio(bus, 0);
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else
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bus->set_mdio(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, read);
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if (read & MDIO_C45)
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bus->set_mdio(bus, ((read >> 1) & 1));
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else
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bus->set_mdio(bus, read);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, !read);
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if (read & MDIO_C45)
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bus->set_mdio(bus, ((read >> 0) & 1));
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else
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bus->set_mdio(bus, !read);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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@ -223,6 +247,135 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
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}
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}
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static int bb_miiphy_cmd_addr(struct bb_miiphy_bus *bus, unsigned phy_addr,
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unsigned int reg_addr)
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{
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unsigned int dev_reg = (reg_addr >> 16) & 0x1F;
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unsigned int reg = reg_addr & 0xFFFF;
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int v, i;
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miiphy_pre (bus, MDIO_C45_ADDR, phy_addr, dev_reg);
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/* send the turnaround (10) */
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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for (i = 15; i >= 0; i--) {
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, ((reg >> i) & 1));
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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}
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/* tri-state our MDIO I/O pin so we can read */
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bus->set_mdc(bus, 0);
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bus->mdio_tristate(bus);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->get_mdio(bus, &v);
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bus->set_mdc(bus, 0);
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return dev_reg;
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}
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/*****************************************************************************
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*
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* Read a MII PHY register V2.
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* This API support C45 support
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* Returns:
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* 0 on success
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*/
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int bb_miiphy_read_v2(const char *devname, unsigned phy_addr,
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unsigned int reg, unsigned short *value)
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{
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short rdreg; /* register working value */
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int v;
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int j; /* counter */
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struct bb_miiphy_bus *bus;
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int phy_reg;
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bus = bb_miiphy_getbus(devname);
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if (bus == NULL) {
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return -1;
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}
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if (value == NULL) {
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puts("NULL value pointer\n");
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return -1;
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}
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if (reg & MII_ADDR_C45) {
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phy_reg = bb_miiphy_cmd_addr(bus, phy_addr, reg);
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miiphy_pre(bus, MDIO_C45_READ, phy_addr, phy_reg);
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} else {
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miiphy_pre(bus, 1, phy_addr, reg);
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}
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/* tri-state our MDIO I/O pin so we can read */
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bus->set_mdc(bus, 0);
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bus->mdio_tristate(bus);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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/* check the turnaround bit: the PHY should be driving it to zero */
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bus->get_mdio(bus, &v);
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if (v != 0) {
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/* puts ("PHY didn't drive TA low\n"); */
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for (j = 0; j < 32; j++) {
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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}
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/* There is no PHY, set value to 0xFFFF and return */
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*value = 0xFFFF;
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return -1;
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}
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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/* read 16 bits of register data, MSB first */
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rdreg = 0;
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for (j = 0; j < 16; j++) {
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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rdreg <<= 1;
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bus->get_mdio(bus, &v);
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rdreg |= (v & 0x1);
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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}
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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*value = rdreg;
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#ifdef DEBUG
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printf ("miiphy_read_v2(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
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#endif
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return 0;
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}
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/*****************************************************************************
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*
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* Read a MII PHY register.
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@ -304,6 +457,71 @@ int bb_miiphy_read(const char *devname, unsigned char addr,
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}
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/*****************************************************************************
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*
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* Write a MII PHY register V2.
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* This API support C45 support
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* Returns:
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* 0 on success
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*/
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int bb_miiphy_write_v2(const char *devname, unsigned int phy_addr,
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unsigned int reg, unsigned short value)
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{
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struct bb_miiphy_bus *bus;
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int j; /* counter */
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unsigned int phy_reg;
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bus = bb_miiphy_getbus(devname);
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if (bus == NULL) {
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/* Bus not found! */
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return -1;
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}
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if (reg & MII_ADDR_C45) {
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phy_reg = bb_miiphy_cmd_addr(bus, phy_addr, reg);
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miiphy_pre(bus, MDIO_C45_WRITE, phy_addr, phy_reg);
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} else {
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miiphy_pre(bus, 0, phy_addr, reg);
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}
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/* send the turnaround (10) */
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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bus->set_mdc(bus, 0);
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bus->set_mdio(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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/* write 16 bits of register data, MSB first */
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for (j = 0; j < 16; j++) {
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bus->set_mdc(bus, 0);
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if ((value & 0x00008000) == 0) {
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bus->set_mdio(bus, 0);
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} else {
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bus->set_mdio(bus, 1);
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}
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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value <<= 1;
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}
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/*
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* Tri-state the MDIO line.
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*/
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bus->mdio_tristate(bus);
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bus->set_mdc(bus, 0);
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bus->delay(bus);
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bus->set_mdc(bus, 1);
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bus->delay(bus);
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return 0;
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}
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/*****************************************************************************
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*
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* Write a MII PHY register.
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@ -90,6 +90,11 @@ int bb_miiphy_read(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value);
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int bb_miiphy_write(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short value);
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int bb_miiphy_read_v2(const char *devname, unsigned int addr,
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unsigned int reg, unsigned short *value);
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int bb_miiphy_write_v2(const char *devname, unsigned int addr,
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unsigned int reg, unsigned short value);
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#endif
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/* phy seed setup */
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