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driver: net: qca8084: added new kconfig for by-pass mode

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Added new config called CONFIG_QCA8084_BYPASS_MODE and moved
all the qca8084 by-pass mode related code under it.

Change-Id: I4157960989cd67576803d494594869265fc81745
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This commit is contained in:
Ram Kumar D 2022-11-29 20:00:30 +05:30 • committed by Gerrit - the friendly Code Review server
parent db766b276c
commit 7f4a4f32de
5 changed files with 85 additions and 55 deletions
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2
configs/ipq5332_defconfig
View file

@ -104,8 +104,8 @@ CONFIG_IPQ_QCA_AQUANTIA_PHY=y
CONFIG_QCA8033_PHY=y
CONFIG_QCA8081_PHY=y
CONFIG_QCA8084_PHY=y
CONFIG_QCA8084_PHY_MODE=y
CONFIG_QCA8084_SWT_MODE=y
CONFIG_QCA8084_BYPASS_MODE=y
CONFIG_ATHRS17C_SWITCH=y
CONFIG_CMD_NET=y

9
drivers/net/Kconfig
View file

@ -137,6 +137,15 @@ config QCA8084_SWT_MODE
help
Enable QCA8084 Switch Mode support.
if QCA8084_SWT_MODE
config QCA8084_BYPASS_MODE
bool "Enable QCA8084 By-pass support"
help
Enable QCA808 By-pass support.
endif # QCA8084_SWT_MODE
config QCA8084_DEBUG
bool "Enable QCA8084 Debug support"
help

28
drivers/net/ipq5332/ipq5332_edma.c
View file

@ -84,18 +84,19 @@ ipq_s17c_swt_cfg_t s17c_swt_cfg;
#endif
static int tftp_acl_our_port;
#ifdef CONFIG_QCA8084_SWT_MODE
static int qca8084_swt_enb = 0;
static int qca8084_chip_detect = 0;
#endif
#endif /* CONFIG_QCA8084_SWT_MODE */
#ifdef CONFIG_QCA8084_PHY_MODE
extern void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr);
extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode);
#endif /* CONFIG_QCA8084_PHY_MODE */
static int qca8084_bypass_enb = 0;
#ifdef CONFIG_QCA8084_BYPASS_MODE
extern void qca8084_bypass_interface_mode_set(u32 interface_mode);
extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode);
static int qca8084_bypass_enb = 0;
#endif /* CONFIG_QCA8084_BYPASS_MODE */
extern void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr);
/*
* EDMA hardware instance
@ -926,7 +927,9 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
continue;
#ifdef CONFIG_QCA8084_SWT_MODE
else if ((qca8084_swt_enb && qca8084_chip_detect) &&
#ifdef CONFIG_QCA8084_BYPASS_MODE
(!(qca8084_bypass_enb & i)) &&
#endif /* CONFIG_QCA8084_BYPASS_MODE */
(phy_info->phy_type == QCA8084_PHY_TYPE)) {
if (!ipq_qca8084_link_update(swt_info))
linkup++;
@ -1119,6 +1122,7 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
}
}
#ifdef CONFIG_QCA8084_BYPASS_MODE
if (phy_info->phy_type == QCA8084_PHY_TYPE) {
if (curr_speed[i] == FAL_SPEED_2500) {
qca8084_phy_sgmii_mode_set(PORT4,
@ -1129,6 +1133,7 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
PHY_SGMII_BASET);
}
}
#endif /* CONFIG_QCA8084_BYPASS_MODE */
ipq5332_port_mac_clock_reset(i);
@ -1735,8 +1740,10 @@ int ipq5332_edma_init(void *edma_board_cfg)
node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
#ifdef CONFIG_QCA8084_SWT_MODE
#ifdef CONFIG_QCA8084_BYPASS_MODE
qca8084_bypass_enb = fdtdec_get_uint(gd->fdt_blob, node,
"qca8084_bypass_enable", 0);
#endif /* CONFIG_QCA8084_BYPASS_MODE */
qca8084_swt_enb = fdtdec_get_uint(gd->fdt_blob, node,
"qca8084_switch_enable", 0);
if (qca8084_swt_enb) {
@ -1940,15 +1947,17 @@ int ipq5332_edma_init(void *edma_board_cfg)
phy_addr);
break;
#endif
#ifdef CONFIG_QCA8084_PHY
#ifdef CONFIG_QCA8084_SWT_MODE
case QCA8084_PHY:
qca8084_chip_detect = 1;
#ifdef CONFIG_QCA8084_BYPASS_MODE
if (qca8084_bypass_enb &&
(phy_addr == PORT4)) {
ipq_qca8084_phy_hw_init(
&ipq5332_edma_dev[i]->ops[phy_id],
phy_addr);
}
#endif /* CONFIG_QCA8084_BYPASS_MODE */
break;
#endif
#ifdef CONFIG_ATHRS17C_SWITCH
@ -1995,8 +2004,11 @@ int ipq5332_edma_init(void *edma_board_cfg)
/** QCA8084 switch specific configurations */
if (qca8084_swt_enb && qca8084_chip_detect) {
#ifdef CONFIG_QCA8084_BYPASS_MODE
if (qca8084_bypass_enb)
qca8084_bypass_interface_mode_set(PHY_SGMII_BASET);
#endif /* CONFIG_QCA8084_BYPASS_MODE */
/*
* Force speed ipq5332 1st port
* for QCA8084 switch mode

59
drivers/net/ipq_common/ipq_qca8084.c
View file

@ -39,15 +39,15 @@ extern void qca8084_port_speed_clock_set(uint32_t qca8084_port_id,
extern void qca8084_port_clk_en_set(uint32_t qca8084_port_id, uint8_t mask,
uint8_t enable);
extern void qca8084_port_clk_reset(uint32_t qca8084_port_id, uint8_t mask);
extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode);
extern u8 qca8081_phy_get_link_status(u32 dev_id, u32 phy_id);
extern u32 qca8081_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex);
extern u32 qca8081_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed);
#ifdef CONFIG_QCA8084_PHY_MODE
extern void qca8084_uniphy_xpcs_autoneg_restart(uint32_t qca8084_port_id);
extern void qca8084_uniphy_xpcs_speed_set(uint32_t qca8084_port_id,
fal_port_speed_t speed);
extern u8 qca8081_phy_get_link_status(u32 dev_id, u32 phy_id);
extern u32 qca8081_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex);
extern u32 qca8081_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed);
extern void qca8084_interface_uqxgmii_mode_set(void);
extern void qca8084_uniphy_uqxgmii_function_reset(uint32_t qca8084_port_id);
#endif /* CONFIG_QCA8084_PHY_MODE */
@ -60,13 +60,17 @@ extern void qca8084_interface_sgmii_mode_set(u32 uniphy_index, u32
qca8084_port_id, mac_config_t *config);
extern uint8_t qca8084_uniphy_mode_check(uint32_t uniphy_index,
qca8084_uniphy_mode_t uniphy_mode);
extern void qca8084_clk_reset(const char *clock_id);
extern void qca8084_clk_disable(const char *clock_id);
extern void qca8084_clk_reset(const char *clock_id);
bool qca8084_port_txfc_forcemode[QCA8084_MAX_PORTS] = {};
bool qca8084_port_rxfc_forcemode[QCA8084_MAX_PORTS] = {};
#endif /* CONFIG_QCA8084_SWT_MODE */
#ifdef CONFIG_QCA8084_BYPASS_MODE
extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode);
#endif /* CONFIG_QCA8084_BYPASS_MODE */
static int qca8084_reg_field_get(u32 reg_addr, u32 bit_offset,
u32 field_len, u8 value[]);
static int qca8084_reg_field_set(u32 reg_addr, u32 bit_offset,
@ -494,6 +498,15 @@ int ipq_qca8084_pinctrl_init(void)
return 0;
}
void qca8084_phy_reset(u32 phy_addr)
{
u16 phy_data;
phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_PHY_CONTROL);
qca8084_phy_reg_write(phy_addr, QCA8084_PHY_CONTROL,
phy_data | QCA8084_CTRL_SOFTWARE_RESET);
}
#ifdef CONFIG_QCA8084_PHY_MODE
void qca8084_phy_ipg_config(uint32_t phy_id, fal_port_speed_t speed)
{
@ -564,6 +577,7 @@ void qca8084_phy_interface_mode_set(void)
/*init pinctrl for phy mode to be added later*/
}
#endif /* CONFIG_QCA8084_PHY_MODE */
void qca8084_cdt_thresh_init(u32 phy_id)
{
@ -614,15 +628,6 @@ void qca8084_phy_modify_debug(u32 phy_addr, u32 debug_reg,
phy_addr, debug_reg, phy_data);
}
void qca8084_phy_reset(u32 phy_addr)
{
u16 phy_data;
phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_PHY_CONTROL);
qca8084_phy_reg_write(phy_addr, QCA8084_PHY_CONTROL,
phy_data | QCA8084_CTRL_SOFTWARE_RESET);
}
void qca8084_phy_adc_edge_set(u32 phy_addr, u32 adc_edge)
{
qca8084_phy_modify_debug(phy_addr,
@ -664,7 +669,6 @@ void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr)
/* invert ADC clock edge as falling edge to fix link issue */
qca8084_phy_adc_edge_set(phy_addr, ADC_FALLING);
}
#endif /* CONFIG_QCA8084_PHY_MODE */
static int qca8084_reg_field_get(u32 reg_addr, u32 bit_offset,
u32 field_len, u8 value[])
@ -788,17 +792,6 @@ static int chip_ver_get(void)
return ret;
}
void qca8084_bypass_interface_mode_set(u32 interface_mode)
{
ipq_qca8084_work_mode_set(QCA8084_PHY_SGMII_UQXGMII_MODE);
qca8084_phy_sgmii_mode_set(PORT4, interface_mode);
pr_debug("ethphy3 software reset\n");
qca8084_phy_reset(PORT4);
/*init pinctrl for phy mode to be added later*/
}
bool qca8084_port_phy_connected(u32 port_id)
{
u32 cpu_bmp = 0x1;
@ -1449,3 +1442,17 @@ void ipq_qca8084_switch_hw_reset(int gpio)
writel(0x2, GPIO_IN_OUT_ADDR(gpio));
}
#endif /* CONFIG_QCA8084_SWT_MODE */
#ifdef CONFIG_QCA8084_BYPASS_MODE
void qca8084_bypass_interface_mode_set(u32 interface_mode)
{
ipq_qca8084_work_mode_set(QCA8084_PHY_SGMII_UQXGMII_MODE);
qca8084_phy_sgmii_mode_set(PORT4, interface_mode);
pr_debug("ethphy3 software reset\n");
qca8084_phy_reset(PORT4);
/*init pinctrl for phy mode to be added later*/
}
#endif /* CONFIG_QCA8084_BYPASS_MODE */

42
drivers/net/ipq_common/ipq_qca8084_interface_ctrl.c
View file

@ -116,7 +116,6 @@ void qca8084_port_speed_clock_set(uint32_t qca8084_port_id,
qca8084_port_clk_rate_set(qca8084_port_id, clk_rate);
}
#ifdef CONFIG_QCA8084_PHY_MODE
void qca8084_ephy_addr_get(uint32_t qca8084_port_id, uint32_t *phy_addr)
{
uint32_t data = 0;
@ -142,6 +141,7 @@ void qca8084_ephy_addr_get(uint32_t qca8084_port_id, uint32_t *phy_addr)
}
}
#ifdef CONFIG_QCA8084_PHY_MODE
static uint16_t qca8084_uniphy_xpcs_mmd_read(uint16_t mmd_num, uint16_t mmd_reg)
{
uint32_t uniphy_xpcs_addr = 0;
@ -182,25 +182,6 @@ static void qca8084_uniphy_xpcs_modify_mmd(uint32_t mmd_num, uint32_t mmd_reg,
qca8084_uniphy_xpcs_mmd_write(mmd_num, mmd_reg, new_phy_data);
}
uint8_t qca8084_uniphy_mode_check(uint32_t uniphy_index,
qca8084_uniphy_mode_t uniphy_mode)
{
uint32_t uniphy_addr = 0;
uint16_t uniphy_mode_ctrl_data = 0;
qca8084_serdes_addr_get(uniphy_index, &uniphy_addr);
uniphy_mode_ctrl_data = qca8084_phy_mmd_read(uniphy_addr,
QCA8084_UNIPHY_MMD1, QCA8084_UNIPHY_MMD1_MODE_CTRL);
if(uniphy_mode_ctrl_data == PHY_INVALID_DATA)
return 0;
if(!(uniphy_mode & uniphy_mode_ctrl_data))
return 0;
return 1;
}
static uint32_t qca8084_uniphy_xpcs_port_to_mmd(uint32_t qca8084_port_id)
{
uint32_t mmd_id = 0;
@ -662,8 +643,28 @@ void qca8084_interface_sgmii_mode_set(u32 uniphy_index, u32 qca8084_port_id, mac
return;
}
uint8_t qca8084_uniphy_mode_check(uint32_t uniphy_index,
qca8084_uniphy_mode_t uniphy_mode)
{
uint32_t uniphy_addr = 0;
uint16_t uniphy_mode_ctrl_data = 0;
qca8084_serdes_addr_get(uniphy_index, &uniphy_addr);
uniphy_mode_ctrl_data = qca8084_phy_mmd_read(uniphy_addr,
QCA8084_UNIPHY_MMD1, QCA8084_UNIPHY_MMD1_MODE_CTRL);
if(uniphy_mode_ctrl_data == PHY_INVALID_DATA)
return 0;
if(!(uniphy_mode & uniphy_mode_ctrl_data))
return 0;
return 1;
}
#endif /* CONFIG_QCA8084_SWT_MODE */
#ifdef CONFIG_QCA8084_BYPASS_MODE
void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode)
{
uint32_t phy_addr_tmp = 0;
@ -693,4 +694,5 @@ void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode)
PORT4, &config);
return;
}
#endif /* CONFIG_QCA8084_BYPASS_MODE */