This change adds cmd_dpr as a common file,
so it will be reused in the future SoC.
dpr support added in Devsoc SoC.
Change-Id: I246a8f51c07c2f6952173bbd72e327ab1119af6e
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Adding a new command mibib_reload to
populate the partition table info from
mibib binary
Change-Id: I3f08fc07ea55f1bbd90dc28d8f459d108f86bc0e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch eliminates to maintain seperate dts file
for mmc flash. It enables flash node based
on machine id.
Change-Id: I67d95db162630a3bc84429e8a9338097e1e24619
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
This change adds support to enable multiple I2C bus on all IPQ
platforms. Removed the device specific changes and updated in
a generic way to support multiple I2C on all the IPQ platforms.
Change-Id: Ie13dd744c6317fc9245bc88781e79a9fb3621a62
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This changes add support for uboot base files.
Change-Id: I5f4b937dec30a27ec6acce6ceada7fbed5d5a41d
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Currently, if atf env is set in the secure board. secure boot
sequence gets bypassed. This is not an expected behaviour. So,
removed support the atf env variable. Instead atf enabled status
can be verified using get_secure_state scm call.
Moreover, as per current design get_secure_state scm call will
not be implemented in ATF in future as well. If its implemented,
Bit 7 should be made to 1.
Change-Id: I0adcfac7bbcb10fe6906fd8a3f10a440ec7080ae
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This patch updates the following:
1) Initializes I2C QUP clocks in U-Boot itself as required
without depending on SBL.
2) Removes all CONFIG_IPQ9574_RUMI references.
Change-Id: I1fb02861a70bd2b024122fff7810c3373cc2e1cd
Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
This change will read the 0:ART partition for calibration data and
apply it to the appropriate registers.
Following sequence added for the same.
1. created scm_read call to read the protected register.
2. added function to read data from ART partition of all flash types
3. added function to apply data to the Caldata register.
Change-Id: I4c769be3cdf664e4c59159851cc211fca53c0f27
Signed-off-by: Ignatius Michael (Jihan) Jihan <quic_mignatiu@quicinc.com>
Add failsafe boot support to recover from system hang.
Signed-off-by: anusha <anusharao@codeaurora.org>
Change-Id: I49e28a4e88aa16e564065d06f8701dc4f6cb3555
When a long string (>255 char) input given to uboot console, RX
stale timeout occurred on UART subsystem due to RXFULL. This in-turn
cause uboot console to stuck.
So, Added a check to catch this scenario and re-start the UART RX
if it occurred.
Change-Id: Ic80c1d5f1178bf2455385c3888a2023ce1dbf6fa
Signed-off-by: Ram Kumar D <ramd@codeaurora.org>
Include SCM call to inform TZ whether HLOS boots from
primary or secondary partition
Change-Id: Ib1fa2b3c12762d1deed5b99f025c83870c142fa6
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
This patch sets the function select as mdc_mdio and also
adds AQUANTIA, QCA80xx PHY ASSERT and DE-ASSERT support.
Change-Id: Ib606b51342df4e80d705271cc661f6fbe1664ed0
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org
Updated the data FIFO size to work with 4K page as well.
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I5d94e50755b0934d1dd6c9c0d2c6759a782f52d5
Added config, dts and initial board support code for ipq9048.
Signed-off-by: anusha <anusharao@codeaurora.org>
Change-Id: Ib4d0da9aedd5c98b02c59dd83d9efa78baada335
This change will skip the bad blocks offsets, if any while writing
into the nand flash duirng crash when dump_to_flash enabled. This
change also verifies whether the dump data is not overwritten into
the next partition.
Signed-off-by: Karthick Shanmugham <kartshan@codeaurora.org>
Change-Id: I0eec4c772a5f5efb3c17bfd1fd3d3d9a5ff85d1d
Encryptio/Decryption
- For encryption/decryption, plain data/
encrypted date has to be written to memory
directly using mw command along with
ivadata, type and mode
- Implemented new uboot command "aes_256"
to receive the memory address where the
above data is written to
- Perfom basic sanity check against the data
received and send them to secure world through
scm calls
- This is supported only for HK/CYP, hence not
implemented for TZ running in 32bit mode
Change-Id: I589a15025cd248cf5792f13ea435c5c5b64c6066
Signed-off-by: Karthick Jeyaraman <kjeyaram@codeaurora.org>
soc_hw_version can used to prevent cross-platform
flashing of single images to prevent board
from getting bricked.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Change-Id: I579489498c8cbbc944b54e3050a319d1e11cb825
This change will enable config for serial training.
This change also fix the the logic to get most appropriate phase
out of passed phase.
This change also add support to read serial training offset from
partition table. Also patching freqency value & phase value to kernel.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibb4a5cd80f16605e8e91bdf6a0c6c484edff1735
This change will enable page_scope_read & multipage_read support for
QPIC.
QPIC version 2.0 onwards , QPIC support page_scope_read &
multipage_read command to enhance the read performance.
In normal page read command SW is needed to write EXEC_CMD register
for each Code word and collect any Status related to that CW before
issueing EXEC_CMD for next CW.
For page_scope read command SW is required to issue EXEC_CMD
only once for a page. Controller HW takes care of Codeword specific
details and automatically returns status associated with each CW to
BAM pipe, dedicated for status deposition.
enabling all bits in NAND_AUTO_STATUS_EN will require 4 data
descriptors of 24 bytes each. This will publish all NANDc status
registers in system memory.
For multipage_read command SW is required to issue EXEC_CMD only
once for all the pages which configured in QPIC_NAND_MULTI_PAGE_CMD
register.
All interrupts will be operational and valid in these modes.
To check the status for each codeword, it is not possible to access
the status registers while the read command is operational in
page_scope & multi_page read modes. Hence, another feature to publish the
status data (for all NAND status registers) by programming the
NAND_AUTO_STATUS_EN register.
For serial NAND:
Read command for page_scope_read = 0x78800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x78400032 (QPIC_NAND_FLASH_CMD)
For Parallel NAND:
Read command for page_scope_read = 0x00800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x00400032 (QPIC_NAND_FLASH_CMD)
Now we fixed maximum data bytes read in one go 128KiB(2KiB page),
256KiB (4KiB page), 512 KiB (8kiB page), because from upper layer
we are getting more than 128KiB data bytes request in one go. if so
just changing the value of "MAX_MULTI_PAGE" macro will increase the
maximum data bytes in one go.
Change-Id: I48eea51ff8f5f79f3490d8a538c295ecc3eeee19
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will add support for serial nand.
QPIC-2.1.1 supports parallel nand as well as serial nand.
QPIC will operate either in parallel configuration or
serial nand. Both can't work together.
This change will support initially four serial nand parts.
MT29F1G01ABBFDWB-IT (Micron-0x2C,0x15, 2K + 128)
GD5F1GQ4RE9IG (Giga Device-0xC8,0xC1, 2K + 128)
GD5F2GQ5REYIH (Giga Device-0xC8,0x22, 2K + 64)
GD5F1GQ4RE9IH (Giga Device-0xC8, 0xC9, 2K + 64)
Device Internal ECC is disabled for all three devices. This change will
enabele QPIC ECC engine.
For MT29F1G01ABBFDWB-IT 4-bit ECC as well 8-bit ECC will be supported.
For GD5F1GQ4RE9IG 4-bit ECC as well 8-bit ECC will be supported.
For GD5F2GQ5REYIH only 4-bit ECC will be supported due to 64-bytes spare.
For GD5F1GQ4RE9IH only 4-bit ECC will be supported due to 64-bytes spare.
Change-Id: I3f38f9c76b7bb235bb335a481fbc42ae1bd00395
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will add support for collecting crashdump as
compressed gzip file, if specified through uboot environment
variable 'dump_compressed'
Change-Id: I0c3fb16bc07aaa0103e75a551477fce13f9e26da
Signed-off-by: Pavithra Palanisamy <pavip@codeaurora.org>
QCN3018 has only 2 cores, the kernel has to bringup
only 2 cores, hence if the SoC is identified as QCN3018
restrict the number of cores using "maxcpus" bootargs
Change-Id: Idafc44c02de302b65f9c9dfc5f77783a91b2c018
Signed-off-by: Sumit Gaur <gaur@codeaurora.org>
moving emmc related macros definitions to ipq807x & ipq40xx
board specific files from common files to avoid
redefined compilar warnings
Change-Id: Ic8d9537535a0b5439d42e8b0b53faadba72c50a3
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This change enables support to collect crashdump files
in connected usb storage device on requirement.
Change-Id: If191bcae5329dd2c9e84035069e4d9b0e73b546b
Signed-off-by: Pavithra Palanisamy <pavip@codeaurora.org>
This change will fix the following compiler warnings for AK and DK targets.
1.Wimplicit-function-declaration
2.Wdiscarded-qualifiers
3.Wstrict-prototypes
4.Wmaybe-uninitialized
5.Wunused-variable
6.Wint-conversion
Change-Id: I364904283172ccb19602ae1b6deceb8c61ea7638
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
