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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
ipq9574: clock: Fix clock configuration
This patch updates the following: 1) Initializes I2C QUP clocks in U-Boot itself as required without depending on SBL. 2) Removes all CONFIG_IPQ9574_RUMI references. Change-Id: I1fb02861a70bd2b024122fff7810c3373cc2e1cd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
This commit is contained in:
Selvam Sathappan Periakaruppan
Gerrit - the friendly Code Review server
parent
d5357b5326
commit
91b2d3dea4
4 changed files with 41 additions and 41 deletions
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@ -19,12 +19,27 @@
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/* I2C clocks configuration */
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#ifdef CONFIG_IPQ9574_I2C
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#define BLSP1_QUP_BASE 0x078B5000
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#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x1802018
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#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x1802024
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#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR 0x180201C
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#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV (0x1F << 0)
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#define GCC_BLSP1_QUP_I2C_OFFSET_INC 0x1000
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#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x1802018
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#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x1802024
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#define GCC_BLSP1_QUP_I2C_APPS_CFG_RCGR(id) ((id < 1) ? \
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(GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR):\
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(GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id)))
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#define GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(id) ((id < 1) ? \
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(GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR):\
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(GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id)))
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#define GCC_BLSP1_QUP_I2C_APPS_CBCR(id) ((id < 1) ? \
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(GCC_BLSP1_QUP1_I2C_APPS_CBCR):\
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(GCC_BLSP1_QUP1_I2C_APPS_CBCR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id)))
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#define I2C_PORT_ID(reg) ((reg - BLSP1_QUP_BASE) / GCC_BLSP1_QUP_I2C_OFFSET_INC)
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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@ -107,10 +107,8 @@ int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_fla
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int get_eth_mac_address(uchar *enetaddr, uint no_of_macs);
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void set_ethmac_addr(void);
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#ifndef CONFIG_IPQ9574_RUMI
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void aquantia_phy_reset_init_done(void);
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void aquantia_phy_reset_init(void);
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#endif
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int bring_sec_core_up(unsigned int cpuid, unsigned int entry, unsigned int arg);
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int is_secondary_core_off(unsigned int cpuid);
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@ -12,28 +12,39 @@
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch-ipq9574/clk.h>
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#include <asm/errno.h>
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#include <fdtdec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_IPQ9574_I2C
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void i2c_clock_config(void)
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void i2c_clock_config()
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{
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#ifndef CONFIG_IPQ9574_RUMI
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int cfg;
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int cfg, i2c_id;
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int i2c_node;
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const u32 *i2c_base;
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/* Configure qup1_i2c_apps_clk_src */
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cfg = (GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL |
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GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR);
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i2c_node = fdt_path_offset(gd->fdt_blob, "i2c0");
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if (i2c_node >= 0) {
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i2c_base = fdt_getprop(gd->fdt_blob, i2c_node, "reg", NULL);
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if (i2c_base) {
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i2c_id = I2C_PORT_ID(fdt32_to_cpu(i2c_base[0]));
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/* Configure qup1_i2c_apps_clk_src */
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cfg = (GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL |
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GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_BLSP1_QUP_I2C_APPS_CFG_RCGR(i2c_id));
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writel(CMD_UPDATE, GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR);
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writel(CMD_UPDATE, GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(i2c_id));
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mdelay(100);
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writel(ROOT_EN, GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(i2c_id));
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/* Configure CBCR */
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writel(CLK_ENABLE, GCC_BLSP1_QUP1_I2C_APPS_CBCR);
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#endif
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/* Configure CBCR */
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writel(CLK_ENABLE, GCC_BLSP1_QUP_I2C_APPS_CBCR(i2c_id));
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}
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}
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}
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#endif
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@ -159,7 +170,6 @@ void qpic_set_clk_rate(unsigned int clk_rate, int blk_type, int req_clk_src_type
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#ifdef CONFIG_PCI_IPQ
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void pcie_v2_clock_init(int pcie_id)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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int cfg, div;
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/* Configure pcie_aux_clk_src */
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@ -224,12 +234,10 @@ void pcie_v2_clock_init(int pcie_id)
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writel(ROOT_EN, GCC_PCIE_REG(GCC_PCIE_RCHNG_CMD_RCGR, pcie_id));
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writel(CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_AUX_CBCR, pcie_id));
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#endif
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}
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void pcie_v2_clock_deinit(int pcie_id)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AUX_CMD_RCGR, 0));
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mdelay(100);
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AHB_CBCR, pcie_id));
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@ -255,14 +263,12 @@ void pcie_v2_clock_deinit(int pcie_id)
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writel(0x0, GCC_ANOC_PCIE3_2LANE_M_CBCR);
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break;
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}
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#endif
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}
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#endif
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(int id)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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int cfg;
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/* Configure usb0_master_clk_src */
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cfg = (GCC_USB0_MASTER_CFG_RCGR_SRC_SEL |
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@ -305,13 +311,11 @@ void usb_clock_init(int id)
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writel((CLK_ENABLE | NOC_HANDSHAKE_FSM_EN),
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GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
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#endif
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}
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void usb_clock_deinit(void)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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/* Disable clocks */
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writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0xcff0, GCC_USB0_MASTER_CBCR);
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@ -320,14 +324,12 @@ void usb_clock_deinit(void)
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writel(0, GCC_USB0_AUX_CBCR);
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writel(0, GCC_ANOC_USB_AXI_CBCR);
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writel(0, GCC_SNOC_USB_CBCR);
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#endif
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}
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#endif
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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int cfg;
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/* Configure sdcc1_apps_clk_src */
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@ -345,15 +347,12 @@ void emmc_clock_init(void)
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writel(readl(GCC_SDCC1_APPS_CBCR) | CLK_ENABLE, GCC_SDCC1_APPS_CBCR);
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udelay(10);
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writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
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#endif
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}
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void emmc_clock_reset(void)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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writel(0x1, GCC_SDCC1_BCR);
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udelay(10);
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writel(0x0, GCC_SDCC1_BCR);
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#endif
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}
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#endif
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@ -108,15 +108,6 @@ void fdt_fixup_qpic(void *blob)
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}
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}
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void qpic_emulation_set_clk(void)
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{
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writel(QPIC_CBCR_VAL, GCC_QPIC_CBCR_ADDR);
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writel(CLK_ENABLE, GCC_QPIC_AHB_CBCR_ADDR);
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writel(CLK_ENABLE, GCC_QPIC_SLEEP_CBCR);
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writel(CLK_ENABLE, GCC_QPIC_IO_MACRO_CBCR);
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}
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void board_nand_init(void)
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{
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#ifdef CONFIG_QPIC_SERIAL
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@ -130,9 +121,6 @@ void board_nand_init(void)
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if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
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printf("QPIC: disabled, skipping initialization\n");
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} else {
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#ifdef CONFIG_IPQ9574_RUMI
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qpic_emulation_set_clk();
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#endif
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qpic_nand_init(NULL);
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}
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#endif
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