mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
ipq5018: Add BT beaconing support
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org> Change-Id: Ibe8dc716d0f4bafbbf1ec7f3b776bb4a6f891f45
This commit is contained in:
Rajkumar Ayyasamy
parent
5f474cadf3
commit
2343ff363f
7 changed files with 341 additions and 1 deletions
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@ -550,6 +550,85 @@ int qca_scm_secure_authenticate(void *cmd_buf, size_t cmd_len)
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return ret;
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}
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#ifdef CONFIG_IPQ_BT_SUPPORT
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int qti_scm_otp(u32 peripheral)
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{
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int ret;
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if (is_scm_armv8())
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{
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struct qca_scm_desc desc = {0};
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desc.arginfo = QCA_SCM_ARGS(1);
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desc.args[0] = peripheral;
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ret = scm_call_64(SCM_SVC_PIL, SCM_CMD_OTP, &desc);
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}
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else
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{
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u32 cmd = peripheral;
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ret = scm_call(SCM_SVC_PIL, SCM_CMD_OTP, &cmd, sizeof(cmd),
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NULL, 0);
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}
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return ret;
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}
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int qti_scm_pas_init_image(u32 peripheral, u32 addr)
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{
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int ret;
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if (is_scm_armv8())
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{
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struct qca_scm_desc desc = {0};
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desc.arginfo = QCA_SCM_ARGS(2, SCM_VAL, SCM_IO_WRITE);
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desc.args[0] = peripheral;
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desc.args[1] = addr;
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ret = scm_call_64(SCM_SVC_PIL, SCM_PAS_INIT_IMAGE_CMD, &desc);
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}
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else
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{
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struct {
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u32 proc;
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u32 image_addr;
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} request;
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request.proc = peripheral;
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request.image_addr = addr;
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ret = scm_call(SCM_SVC_PIL, SCM_PAS_INIT_IMAGE_CMD, &request,
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sizeof(request), NULL, 0);
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}
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return ret;
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}
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int qti_pas_and_auth_reset(u32 peripheral)
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{
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int ret;
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u32 cmd = peripheral;
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if (is_scm_armv8())
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{
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struct qca_scm_desc desc = {0};
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desc.arginfo = QCA_SCM_ARGS(1);
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desc.args[0] = peripheral;
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ret = scm_call_64(SCM_SVC_PIL, SCM_PAS_AUTH_AND_RESET_CMD, &desc);
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}
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else
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{
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ret = scm_call(SCM_SVC_PIL, SCM_PAS_AUTH_AND_RESET_CMD, &cmd, sizeof(cmd),
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NULL, 0);
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}
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return ret;
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}
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#endif
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#else
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int qca_scm_call(u32 svc_id, u32 cmd_id, void *buf, size_t len)
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{
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@ -14,6 +14,7 @@
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#ifndef IPQ5018_CLK_H
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#define IPQ5018_CLK_H
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#define CLK_ENABLE 0x1
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/* I2C clocks configuration */
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#ifdef CONFIG_IPQ5018_I2C
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@ -26,8 +27,14 @@
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define CLK_ENABLE 0x1
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void i2c_clock_config(void);
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#endif
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#ifdef CONFIG_IPQ_BT_SUPPORT
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#define GCC_BTSS_LPO_CBCR 0x181C004
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void enable_btss_lpo_clk(void);
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#endif
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#endif /*IPQ5018_CLK_H*/
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@ -34,6 +34,12 @@
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#define SCM_SVC_ID_SHIFT 0xA
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#define IS_CALL_AVAIL_CMD 0x1
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#ifdef CONFIG_IPQ_BT_SUPPORT
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#define SCM_PAS_INIT_IMAGE_CMD 0x1
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#define SCM_PAS_AUTH_AND_RESET_CMD 0x5
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#define SCM_CMD_OTP 0x15
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#endif
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/* scm_v8 */
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#define SCM_VAL 0x0
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#define SCM_IO_READ 0x1
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@ -130,6 +136,11 @@ int is_scm_sec_auth_available(u32 svc_id, u32 cmd_id);
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#ifdef CONFIG_IPQ_TZT
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int qca_scm(u32 svc_id, u32 cmd_id, u32 ownr_id, u32 *addr, u32 len);
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#endif
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#ifdef CONFIG_IPQ_BT_SUPPORT
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int qti_scm_otp(u32 peripheral);
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int qti_scm_pas_init_image(u32 peripheral, u32 addr);
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int qti_pas_and_auth_reset(u32 peripheral);
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#endif
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#define MAX_QCA_SCM_RETS 3
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#define MAX_QCA_SCM_ARGS 10
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#define SCM_READ_OP 1
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@ -35,3 +35,9 @@ void i2c_clock_config(void)
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}
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#endif
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#ifdef CONFIG_IPQ_BT_SUPPORT
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void enable_btss_lpo_clk(void)
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{
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writel(CLK_ENABLE, GCC_BTSS_LPO_CBCR);
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}
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#endif
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@ -32,6 +32,12 @@
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#ifdef CONFIG_QPIC_NAND
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#include <asm/arch-qca-common/qpic_nand.h>
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#endif
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#ifdef CONFIG_IPQ_BT_SUPPORT
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#include <malloc.h>
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#include "bt.h"
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#include "bt_binary_array.h"
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#include <linux/compat.h>
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#endif
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#define DLOAD_MAGIC_COOKIE 0x10
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@ -477,6 +483,180 @@ void fdt_fixup_auto_restart(void *blob)
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return;
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}
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#ifdef CONFIG_IPQ_BT_SUPPORT
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unsigned char hci_reset[] =
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{0x01, 0x03, 0x0c, 0x00};
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unsigned char adv_data[] =
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{0x01, 0X08, 0X20, 0X20, 0X1F, 0X0A, 0X09, 0X71,
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0X75, 0X61, 0X6c, 0X63, 0X6f, 0X6d, 0X6d, 0X00,
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0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00,
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0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00,
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0X00, 0X00, 0X00, 0X00};
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unsigned char set_interval[] =
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{0X01, 0X06, 0X20, 0X0F, 0X20, 0X00, 0X20, 0X00,
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0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00,
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0X00, 0X07, 0X00};
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unsigned char start_beacon[] =
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{0x01, 0x0A, 0x20, 0x01, 0x01};
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unsigned char *hci_cmds[] = {
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hci_reset,
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adv_data,
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set_interval,
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start_beacon
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};
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int wait_for_bt_event(struct bt_descriptor *btDesc, u8 bt_wait)
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{
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int val, timeout = 0;
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do{
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udelay(10);
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bt_ipc_worker(btDesc);
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if (bt_wait == BT_WAIT_FOR_START)
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val = !atomic_read(&btDesc->state);
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else
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val = atomic_read(&btDesc->tx_in_progress);
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if (timeout++ >= BT_TIMEOUT_US/10) {
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printf(" %s timed out \n", __func__);
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return -ETIMEDOUT;
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}
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} while (val);
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return 0;
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}
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static int initialize_nvm(struct bt_descriptor *btDesc,
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void *fileaddr, u32 filesize)
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{
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unsigned char *buffer = fileaddr;
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int bytes_read = 0, bytes_consumed = 0, ret;
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HCI_Packet_t *hci_packet = NULL;
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while(bytes_consumed < filesize )
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{
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bytes_read = (filesize - bytes_consumed) > NVM_SEGMENT_SIZE ?
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NVM_SEGMENT_SIZE : filesize - bytes_consumed;
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/* Constructing a HCI Packet to write NVM Segments to BTSS */
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hci_packet = (HCI_Packet_t*)malloc(sizeof(HCI_Packet_t) +
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NVM_SEGMENT_SIZE);
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if(!hci_packet)
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{
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printf("Cannot allocate memory to HCI Packet \n");
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return -ENOMEM;
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}
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/* Initializing HCI Packet Header */
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hci_packet->HCIPacketType = ptHCICommandPacket;
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/* Populating TLV Request Packet in HCI */
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LE_UNALIGNED(&(hci_packet->HCIPayload.opcode), TLV_REQ_OPCODE);
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LE_UNALIGNED(&(hci_packet->HCIPayload.parameter_total_length),
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(bytes_read + DATA_REMAINING_LENGTH));
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hci_packet->HCIPayload.command_request = TLV_COMMAND_REQUEST;
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hci_packet->HCIPayload.tlv_segment_length = bytes_read;
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memcpy(hci_packet->HCIPayload.tlv_segment_data, buffer,
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bytes_read);
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bt_ipc_sendmsg(btDesc, (u8*)hci_packet,
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sizeof(HCI_Packet_t) + bytes_read);
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free(hci_packet);
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bytes_consumed += bytes_read;
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buffer = fileaddr + bytes_consumed;
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ret = wait_for_bt_event(btDesc, BT_WAIT_FOR_TX_COMPLETE);
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if(ret || *((u8 *)btDesc->buf + TLV_RESPONSE_STATUS_INDEX) != 0)
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{
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printf( "\n NVM download failed\n");
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if (!ret) {
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kfree(btDesc->buf);
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btDesc->buf = NULL;
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}
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return -EINVAL;
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}
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kfree(btDesc->buf);
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btDesc->buf = NULL;
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}
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printf("NVM download successful \n");
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bt_ipc_worker(btDesc);
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return 0;
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}
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int send_bt_hci_cmds(struct bt_descriptor *btDesc)
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{
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int ret, i;
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int count = sizeof hci_cmds/ sizeof(unsigned char *);
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for (i = 0; i < count; i++) {
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bt_ipc_sendmsg(btDesc, hci_cmds[i], sizeof hci_cmds[i]);
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ret = wait_for_bt_event(btDesc, BT_WAIT_FOR_TX_COMPLETE);
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if (ret)
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return ret;
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/*btDesc->buf will have response data with length btDesc->len*/
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kfree(btDesc->buf);
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btDesc->buf = NULL;
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}
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return 0;
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}
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int bt_init(void)
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{
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struct bt_descriptor *btDesc;
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int ret;
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btDesc = kzalloc(sizeof(*btDesc), GFP_KERNEL);
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if (!btDesc)
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return -ENOMEM;
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bt_ipc_init(btDesc);
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enable_btss_lpo_clk();
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ret = qti_scm_pas_init_image(PAS_ID, (u32)bt_fw_patchmdt);
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if (ret) {
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printf("patch auth failed\n");
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return ret;
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}
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printf("patch authenticated successfully\n");
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memcpy((void*)BT_RAM_PATCH, (void*)bt_fw_patchb02,
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sizeof bt_fw_patchb02);
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ret = qti_pas_and_auth_reset(PAS_ID);
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if (ret) {
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printf("BT out of reset failed\n");
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return ret;
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}
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ret = wait_for_bt_event(btDesc, BT_WAIT_FOR_START);
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if (ret)
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return ret;
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ret = initialize_nvm(btDesc, (void*)mpnv10bin, sizeof mpnv10bin);
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if (ret)
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return ret;
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ret = wait_for_bt_event(btDesc, BT_WAIT_FOR_START);
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if (ret)
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return ret;
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send_bt_hci_cmds(btDesc);
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return 0;
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}
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#endif
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void reset_crashdump(void)
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{
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unsigned int ret = 0;
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@ -588,6 +768,9 @@ void board_nand_init(void)
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}
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#endif
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#ifdef CONFIG_IPQ_BT_SUPPORT
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bt_init();
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#endif
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#ifdef CONFIG_QCA_SPI
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int gpio_node;
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gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
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@ -588,4 +588,56 @@ typedef enum {
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SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
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} smem_mem_type_t;
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#ifdef CONFIG_IPQ_BT_SUPPORT
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#define NVM_SEGMENT_SIZE 243
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#define TLV_REQ_OPCODE 0xFC00
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#define TLV_COMMAND_REQUEST 0x1E
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#define DATA_REMAINING_LENGTH 2
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#define TLV_RESPONSE_PACKET_SIZE 8
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#define TLV_RESPONSE_STATUS_INDEX 6
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#define PACKED_STRUCT __attribute__((__packed__))
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#define LE_UNALIGNED(x, y) \
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{ \
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((u8 *)(x))[0] = ((u8)(((u32)(y)) & 0xFF)); \
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((u8 *)(x))[1] = ((u8)((((u32)(y)) >> 8) & 0xFF)); \
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}
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typedef enum
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{
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ptHCICommandPacket = 0x01, /* Simple HCI Command Packet */
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ptHCIACLDataPacket = 0x02, /* HCI ACL Data Packet Type. */
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ptHCISCODataPacket = 0x03, /* HCI SCO Data Packet Type. */
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ptHCIeSCODataPacket= 0x03, /* HCI eSCO Data Packet Type. */
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ptHCIEventPacket = 0x04, /* HCI Event Packet Type. */
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ptHCIAdditional = 0x05 /* Starting Point for Additional*/
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} HCI_PacketType_t;
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typedef struct _tlv_download_req
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{
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u16 opcode;
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u8 parameter_total_length;
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u8 command_request;
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u8 tlv_segment_length;
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u8 tlv_segment_data[0];
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} PACKED_STRUCT tlv_download_req;
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typedef struct _tagHCI_Packet_t
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{
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u8 HCIPacketType;
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tlv_download_req HCIPayload;
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} PACKED_STRUCT HCI_Packet_t;
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typedef enum {
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BT_WAIT_FOR_START = 0,
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BT_WAIT_FOR_TX_COMPLETE = 1,
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BT_WAIT_FOR_STOP = 2,
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} bt_wait;
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#define BT_TIMEOUT_US 50000
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int bt_init(void);
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#endif
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#endif /* _IPQ5018_CDP_H_ */
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@ -425,4 +425,6 @@ extern loff_t board_env_size;
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#define INTERNAL_96MHZ
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/*#define CONFIG_IPQ_BT_SUPPORT*/
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#endif /* _IPQ5018_H */
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