mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
qca: arm: devsoc: add support for devsoc
This changes add support for uboot base files. Change-Id: I5f4b937dec30a27ec6acce6ceada7fbed5d5a41d Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy
Gerrit - the friendly Code Review server
parent
b30791ddf4
commit
2e8afabbcb
19 changed files with 1265 additions and 3 deletions
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@ -461,6 +461,14 @@ config ARCH_IPQ5018
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select SYS_GENERIC_BOARD
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select QCA_COMMON
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config ARCH_DEVSOC
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bool "QCA, DEVSOC"
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select DM
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select DM_SERIAL
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select CPU_V7
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select SYS_GENERIC_BOARD
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select QCA_COMMON
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config ARCH_IPQ6018
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bool "QCA, IPQ6018"
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select DM
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@ -866,6 +874,7 @@ source "board/hisilicon/hikey/Kconfig"
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source "board/imx31_phycore/Kconfig"
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source "board/ipq40xx/Kconfig"
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source "board/ipq5018/Kconfig"
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source "board/devsoc/Kconfig"
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source "board/ipq6018/Kconfig"
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source "board/ipq806x/Kconfig"
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source "board/ipq9574/Kconfig"
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@ -48,7 +48,8 @@ save_boot_params_ret:
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msr cpsr,r0
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#if defined (CONFIG_ARCH_IPQ807x) || defined (CONFIG_ARCH_IPQ6018) \
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|| defined (CONFIG_ARCH_IPQ5018) || defined (CONFIG_ARCH_IPQ9574)
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|| defined (CONFIG_ARCH_IPQ5018) || defined (CONFIG_ARCH_DEVSOC) \
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|| defined (CONFIG_ARCH_IPQ9574)
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/* Setup CP15 barrier */
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mrc p15, 0, r0, c1, c0, 0 @Read SCTLR to r0
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orr r0, r0, #0x20 @set the cp15 barrier enable bit
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@ -91,6 +91,8 @@ dtb-$(CONFIG_ARCH_IPQ5018) += ipq5018-db-mp02.1.dtb \
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ipq5018-db-mp03.1.dtb
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endif
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dtb-$(CONFIG_ARCH_DEVSOC) += devsoc-emulation.dtb
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dtb-$(CONFIG_ARCH_IPQ6018) += ipq6018-cp01-c1.dtb \
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ipq6018-cp02-c1.dtb \
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ipq6018-cp03-c1.dtb \
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53
arch/arm/dts/devsoc-emulation.dts
Normal file
53
arch/arm/dts/devsoc-emulation.dts
Normal file
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "devsoc-soc.dtsi"
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/ {
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model ="QCA, DEVSOC-EMULATION";
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compatible = "qca,devsoc", "qca,devsoc-emulation";
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machid = <0xF050000>;
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config_name = "config@emulation";
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aliases {
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console = "/serial@78AF000";
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};
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console: serial@78AF000 {
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status = "ok";
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serial_gpio {
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blsp0_uart_rx {
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gpio = <18>;
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func = <1>;
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pull = <GPIO_PULL_DOWN>;
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oe = <GPIO_OE_DISABLE>;
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drvstr = <GPIO_8MA>;
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od_en = <GPIO_OD_DISABLE>;
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};
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blsp0_uart_tx {
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gpio = <19>;
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func = <1>;
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pull = <GPIO_NO_PULL>;
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oe = <GPIO_OE_DISABLE>;
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drvstr = <GPIO_8MA>;
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od_en = <GPIO_OD_DISABLE>;
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};
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};
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};
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timer {
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gpt_freq_hz = <240000>;
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};
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};
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75
arch/arm/dts/devsoc-soc.dtsi
Normal file
75
arch/arm/dts/devsoc-soc.dtsi
Normal file
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@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/qcom/gpio-devsoc.h>
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/ {
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serial@78AF000 {
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compatible = "qca,ipq-uartdm";
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reg = <0x78af000 0x200>;
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m_value = <0x24>;
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n_value = <0xC31A>;
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d_value = <0xC2F6>;
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bit_rate = <0xff>;
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status = "disabled";
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};
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timer {
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gcnt_cntcv_lo = <0x4a2000>;
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gcnt_cntcv_hi = <0x4a2004>;
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gpt_freq_hz = <24000000>;
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timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
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};
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spi {
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compatible = "qcom,spi-qup-v2.7.0";
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wr_pipe_0 = <4>;
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rd_pipe_0 = <5>;
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wr_pipe_1 = <6>;
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rd_pipe_1 = <7>;
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wr_pipe_2 = <8>;
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rd_pipe_2 = <9>;
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status = "ok";
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spi_gpio {
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blsp0_spi_clk {
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gpio = <14>;
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func = <1>;
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pull = <GPIO_NO_PULL>;
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oe = <GPIO_OE_ENABLE>;
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drvstr = <GPIO_2MA>;
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};
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blsp0_spi_mosi {
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gpio = <15>;
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func = <1>;
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pull = <GPIO_NO_PULL>;
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oe = <GPIO_OE_ENABLE>;
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drvstr = <GPIO_2MA>;
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};
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blsp0_spi_miso {
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gpio = <16>;
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func = <1>;
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pull = <GPIO_NO_PULL>;
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drvstr = <GPIO_2MA>;
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};
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blsp0_spi_cs {
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gpio = <17>;
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func = <1>;
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oe = <GPIO_OE_ENABLE>;
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drvstr = <GPIO_2MA>;
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};
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};
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};
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};
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64
arch/arm/include/asm/arch-devsoc/clk.h
Normal file
64
arch/arm/include/asm/arch-devsoc/clk.h
Normal file
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@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DEVSOC_CLK_H
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#define _DEVSOC_CLK_H
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#include <asm/arch-qca-common/uart.h>
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/*
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* UART registers
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*/
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#define GCC_BLSP1_UART1_BCR 0x1802028
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#define GCC_BLSP1_UART2_BCR 0x1803028
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#define GCC_BLSP1_UART3_BCR 0x1804028
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#define GCC_BLSP1_UART_BCR(id) ((id < 1) ? \
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(GCC_BLSP1_UART1_BCR):\
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(GCC_BLSP1_UART1_BCR + (0x1000 * id)))
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#define GCC_BLSP1_UART_APPS_CMD_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x04)
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#define GCC_BLSP1_UART_APPS_CFG_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x08)
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#define GCC_BLSP1_UART_APPS_M(id) (GCC_BLSP1_UART_BCR(id) + 0x0c)
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#define GCC_BLSP1_UART_APPS_N(id) (GCC_BLSP1_UART_BCR(id) + 0x10)
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#define GCC_BLSP1_UART_APPS_D(id) (GCC_BLSP1_UART_BCR(id) + 0x14)
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#define GCC_BLSP1_UART_APPS_CBCR(id) (GCC_BLSP1_UART_BCR(id) + 0x18)
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#define GCC_UART_CFG_RCGR_MODE_MASK 0x3000
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#define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700
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#define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F
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#define GCC_UART_CFG_RCGR_MODE_SHIFT 12
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#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
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#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
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#define UART_RCGR_SRC_SEL 0x1
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#define UART_RCGR_SRC_DIV 0x0
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#define UART_RCGR_MODE 0x2
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#define UART_CMD_RCGR_UPDATE 0x1
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#define UART_CMD_RCGR_ROOT_EN 0x2
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#define UART_CBCR_CLK_ENABLE 0x1
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#define NOT_2D(two_d) (~two_d)
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#define NOT_N_MINUS_M(n,m) (~(n - m))
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define CLK_ENABLE 0x1
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int uart_clock_config(struct ipq_serial_platdata *plat);
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#endif /*IPQ9574_CLK_H*/
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@ -21,6 +21,10 @@
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#include <asm/arch-ipq5018/clk.h>
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#endif
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#ifdef CONFIG_ARCH_DEVSOC
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#include <asm/arch-devsoc/clk.h>
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#endif
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#ifdef CONFIG_ARCH_IPQ6018
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#include <asm/arch-ipq6018/clk.h>
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#endif
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@ -37,7 +41,6 @@
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#include <asm/arch-ipq40xx/clk.h>
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#endif
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#ifdef CONFIG_ARCH_IPQ806x
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#include <asm/arch-ipq806x/clk.h>
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#endif
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15
board/devsoc/Kconfig
Normal file
15
board/devsoc/Kconfig
Normal file
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@ -0,0 +1,15 @@
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if ARCH_DEVSOC
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config SYS_CPU
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default "devsoc"
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config SYS_BOARD
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default "devsoc"
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config SYS_VENDOR
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default "qca/arm"
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config SYS_CONFIG_NAME
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default "devsoc"
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endif
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4
board/qca/arm/devsoc/Makefile
Normal file
4
board/qca/arm/devsoc/Makefile
Normal file
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@ -0,0 +1,4 @@
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ccflags-y += -I$(srctree)/board/qca/arm/devsoc
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cppflags-y += -I$(srctree)/board/qca/arm/devsoc
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obj-y := devsoc.o
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obj-y += clock.o
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82
board/qca/arm/devsoc/clock.c
Normal file
82
board/qca/arm/devsoc/clock.c
Normal file
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@ -0,0 +1,82 @@
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/*
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* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch-devsoc/clk.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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static void uart_configure_mux(u8 id)
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{
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unsigned long cfg_rcgr;
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cfg_rcgr = readl(GCC_BLSP1_UART_APPS_CFG_RCGR(id));
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/* Clear mode, src sel, src div */
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cfg_rcgr &= ~(GCC_UART_CFG_RCGR_MODE_MASK |
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GCC_UART_CFG_RCGR_SRCSEL_MASK |
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GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART_RCGR_SRC_SEL << GCC_UART_CFG_RCGR_SRCSEL_SHIFT)
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& GCC_UART_CFG_RCGR_SRCSEL_MASK);
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cfg_rcgr |= ((UART_RCGR_SRC_DIV << GCC_UART_CFG_RCGR_SRCDIV_SHIFT)
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& GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART_RCGR_MODE << GCC_UART_CFG_RCGR_MODE_SHIFT)
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& GCC_UART_CFG_RCGR_MODE_MASK);
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writel(cfg_rcgr, GCC_BLSP1_UART_APPS_CFG_RCGR(id));
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}
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static int uart_trigger_update(u8 id)
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{
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unsigned long cmd_rcgr;
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int timeout = 0;
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cmd_rcgr = readl(GCC_BLSP1_UART_APPS_CMD_RCGR(id));
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cmd_rcgr |= UART_CMD_RCGR_UPDATE | UART_CMD_RCGR_ROOT_EN;
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writel(cmd_rcgr, GCC_BLSP1_UART_APPS_CMD_RCGR(id));
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while (readl(GCC_BLSP1_UART_APPS_CMD_RCGR(id)) & UART_CMD_RCGR_UPDATE) {
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if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) {
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printf("Timeout waiting for UART clock update\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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return 0;
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}
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int uart_clock_config(struct ipq_serial_platdata *plat)
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{
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unsigned long cbcr_val;
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int ret;
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uart_configure_mux(plat->port_id);
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writel(plat->m_value, GCC_BLSP1_UART_APPS_M(plat->port_id));
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writel(NOT_N_MINUS_M(plat->n_value, plat->m_value),
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GCC_BLSP1_UART_APPS_N(plat->port_id));
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writel(NOT_2D(plat->d_value), GCC_BLSP1_UART_APPS_D(plat->port_id));
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ret = uart_trigger_update(plat->port_id);
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if (ret)
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return ret;
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cbcr_val = readl(GCC_BLSP1_UART_APPS_CBCR(plat->port_id));
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cbcr_val |= UART_CBCR_CLK_ENABLE;
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writel(cbcr_val, GCC_BLSP1_UART_APPS_CBCR(plat->port_id));
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return 0;
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}
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137
board/qca/arm/devsoc/devsoc.c
Normal file
137
board/qca/arm/devsoc/devsoc.c
Normal file
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@ -0,0 +1,137 @@
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <environment.h>
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#include <fdtdec.h>
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#include <asm/arch-qca-common/gpio.h>
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#include <asm/arch-qca-common/uart.h>
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#include <asm/arch-qca-common/scm.h>
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#include <asm/arch-qca-common/iomap.h>
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#include <devsoc.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern int ipq_spi_init(u16);
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const char *rsvd_node = "/reserved-memory";
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const char *del_node[] = {"uboot",
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"sbl",
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NULL};
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const add_node_t add_fdt_node[] = {{}};
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void qca_serial_init(struct ipq_serial_platdata *plat)
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{
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int ret;
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if (plat->gpio_node >= 0) {
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qca_gpio_init(plat->gpio_node);
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}
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plat->port_id = UART_PORT_ID(plat->reg_base);
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ret = uart_clock_config(plat);
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if (ret)
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printf("UART clock config failed %d\n", ret);
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return;
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}
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void reset_board(void)
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{
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run_command("reset", 0);
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}
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int set_uuid_bootargs(char *boot_args, char *part_name, int buflen,
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bool gpt_flag)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__weak int ipq_get_tz_version(char *version_name, int buf_size)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int apps_iscrashed(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_crashdump(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void psci_sys_reset(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void qti_scm_pshold(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void reset_cpu(unsigned long a)
|
||||
{
|
||||
reset_crashdump();
|
||||
if (is_scm_armv8()) {
|
||||
psci_sys_reset();
|
||||
} else {
|
||||
qti_scm_pshold();
|
||||
}
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
void board_nand_init(void)
|
||||
{
|
||||
#ifdef CONFIG_QCA_SPI
|
||||
int gpio_node;
|
||||
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
|
||||
if (gpio_node >= 0) {
|
||||
qca_gpio_init(gpio_node);
|
||||
ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void enable_caches(void)
|
||||
{
|
||||
icache_enable();
|
||||
}
|
||||
|
||||
void disable_caches(void)
|
||||
{
|
||||
icache_disable();
|
||||
}
|
||||
|
||||
unsigned long timer_read_counter(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void set_flash_secondary_type(qca_smem_flash_info_t *smem)
|
||||
{
|
||||
return;
|
||||
};
|
||||
158
board/qca/arm/devsoc/devsoc.h
Normal file
158
board/qca/arm/devsoc/devsoc.h
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DEVSOC_CDP_H_
|
||||
#define _DEVSOC_CDP_H_
|
||||
|
||||
#include <configs/devsoc.h>
|
||||
#include <asm/u-boot.h>
|
||||
#include <asm/arch-qca-common/qca_common.h>
|
||||
#include "phy.h"
|
||||
|
||||
extern const char *rsvd_node;
|
||||
extern const char *del_node[];
|
||||
extern const add_node_t add_fdt_node[];
|
||||
|
||||
/*
|
||||
* weak function
|
||||
*/
|
||||
|
||||
__weak void aquantia_phy_reset_init_done(void) {}
|
||||
__weak void aquantia_phy_reset_init(void) {}
|
||||
__weak void qgic_init(void) {}
|
||||
__weak void handle_noc_err(void) {}
|
||||
__weak void board_pcie_clock_init(int id) {}
|
||||
__weak void ubi_power_collapse(void) {}
|
||||
|
||||
|
||||
#define KERNEL_AUTH_CMD 0x13
|
||||
#define SCM_CMD_SEC_AUTH 0x15
|
||||
|
||||
#define BLSP1_UART0_BASE 0x078AF000
|
||||
#define UART_PORT_ID(reg) ((reg - BLSP1_UART0_BASE) / 0x1000)
|
||||
|
||||
|
||||
/*
|
||||
* SMEM
|
||||
*/
|
||||
#ifdef CONFIG_SMEM_VERSION_C
|
||||
#define RAM_PART_NAME_LENGTH 16
|
||||
/**
|
||||
* Number of RAM partition entries which are usable by APPS.
|
||||
*/
|
||||
#define RAM_NUM_PART_ENTRIES 32
|
||||
struct ram_partition_entry
|
||||
{
|
||||
char name[RAM_PART_NAME_LENGTH]; /**< Partition name, unused for now */
|
||||
u64 start_address; /**< Partition start address in RAM */
|
||||
u64 length; /**< Partition length in RAM in Bytes */
|
||||
u32 partition_attribute; /**< Partition attribute */
|
||||
u32 partition_category; /**< Partition category */
|
||||
u32 partition_domain; /**< Partition domain */
|
||||
u32 partition_type; /**< Partition type */
|
||||
u32 num_partitions; /**< Number of partitions on device */
|
||||
u32 hw_info; /**< hw information such as type and frequency */
|
||||
u8 highest_bank_bit; /**< Highest bit corresponding to a bank */
|
||||
u8 reserve0; /**< Reserved for future use */
|
||||
u8 reserve1; /**< Reserved for future use */
|
||||
u8 reserve2; /**< Reserved for future use */
|
||||
u32 reserved5; /**< Reserved for future use */
|
||||
u64 available_length; /**< Available Partition length in RAM in Bytes */
|
||||
};
|
||||
|
||||
struct usable_ram_partition_table
|
||||
{
|
||||
u32 magic1; /**< Magic number to identify valid RAM partition table */
|
||||
u32 magic2; /**< Magic number to identify valid RAM partition table */
|
||||
u32 version; /**< Version number to track structure definition changes
|
||||
and maintain backward compatibilities */
|
||||
u32 reserved1; /**< Reserved for future use */
|
||||
|
||||
u32 num_partitions; /**< Number of RAM partition table entries */
|
||||
|
||||
u32 reserved2; /** < Added for 8 bytes alignment of header */
|
||||
|
||||
/** RAM partition table entries */
|
||||
struct ram_partition_entry ram_part_entry[RAM_NUM_PART_ENTRIES];
|
||||
};
|
||||
#endif
|
||||
|
||||
struct smem_ram_ptn {
|
||||
char name[16];
|
||||
unsigned long long start;
|
||||
unsigned long long size;
|
||||
|
||||
/* RAM Partition attribute: READ_ONLY, READWRITE etc. */
|
||||
unsigned attr;
|
||||
|
||||
/* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
|
||||
unsigned category;
|
||||
|
||||
/* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
|
||||
unsigned domain;
|
||||
|
||||
/* RAM Partition type: system, bootloader, appsboot, apps etc. */
|
||||
unsigned type;
|
||||
|
||||
/* reserved for future expansion without changing version number */
|
||||
unsigned reserved2, reserved3, reserved4, reserved5;
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
struct smem_ram_ptable {
|
||||
#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
|
||||
#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
|
||||
unsigned magic[2];
|
||||
unsigned version;
|
||||
unsigned reserved1;
|
||||
unsigned len;
|
||||
unsigned buf;
|
||||
struct smem_ram_ptn parts[32];
|
||||
} __attribute__ ((__packed__));
|
||||
|
||||
typedef enum {
|
||||
SMEM_SPINLOCK_ARRAY = 7,
|
||||
SMEM_AARM_PARTITION_TABLE = 9,
|
||||
SMEM_HW_SW_BUILD_ID = 137,
|
||||
SMEM_USABLE_RAM_PARTITION_TABLE = 402,
|
||||
SMEM_POWER_ON_STATUS_INFO = 403,
|
||||
SMEM_MACHID_INFO_LOCATION = 425,
|
||||
SMEM_IMAGE_VERSION_TABLE = 469,
|
||||
SMEM_BOOT_FLASH_TYPE = 498,
|
||||
SMEM_BOOT_FLASH_INDEX = 499,
|
||||
SMEM_BOOT_FLASH_CHIP_SELECT = 500,
|
||||
SMEM_BOOT_FLASH_BLOCK_SIZE = 501,
|
||||
SMEM_BOOT_FLASH_DENSITY = 502,
|
||||
SMEM_BOOT_DUALPARTINFO = 503,
|
||||
SMEM_PARTITION_TABLE_OFFSET = 504,
|
||||
SMEM_SPI_FLASH_ADDR_LEN = 505,
|
||||
SMEM_RUNTIME_FAILSAFE_INFO = 507,
|
||||
SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
|
||||
SMEM_LAST_VALID_TYPE = SMEM_RUNTIME_FAILSAFE_INFO,
|
||||
SMEM_MAX_SIZE = SMEM_RUNTIME_FAILSAFE_INFO + 1,
|
||||
} smem_mem_type_t;
|
||||
|
||||
/*
|
||||
* function declaration
|
||||
*/
|
||||
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
|
||||
void reset_crashdump(void);
|
||||
void reset_board(void);
|
||||
int ipq_get_tz_version(char *version_name, int buf_size);
|
||||
void ipq_fdt_fixup_socinfo(void *blob);
|
||||
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
|
||||
int smem_ram_ptable_init_v2(
|
||||
struct usable_ram_partition_table *usable_ram_partition_table);
|
||||
|
||||
#endif /* _DEVSOC_CDP_H_ */
|
||||
346
configs/devsoc_defconfig
Normal file
346
configs/devsoc_defconfig
Normal file
|
|
@ -0,0 +1,346 @@
|
|||
# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License version 2 and
|
||||
# only version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
|
||||
CONFIG_ARM=y
|
||||
CONFIG_HAS_VBAR=y
|
||||
CONFIG_CPU_V7=y
|
||||
CONFIG_ARCH_DEVSOC=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x400
|
||||
CONFIG_SYS_MALLOC_F=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE=""
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
# CONFIG_FIT_SIGNATURE is not set
|
||||
CONFIG_SYS_EXTRA_OPTIONS=""
|
||||
CONFIG_SYS_PROMPT="devsoc# "
|
||||
|
||||
#
|
||||
# Tiny support
|
||||
#
|
||||
# CONFIG_IPQ_TINY is not set
|
||||
|
||||
#
|
||||
# Info commands
|
||||
#
|
||||
CONFIG_CMD_BDI=y
|
||||
CONFIG_CMD_CONSOLE=y
|
||||
|
||||
#
|
||||
# Boot commands
|
||||
#
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
CONFIG_CMD_BOOTM=y
|
||||
CONFIG_CMD_GO=y
|
||||
CONFIG_CMD_RUN=y
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
|
||||
#
|
||||
# Environment commands
|
||||
#
|
||||
CONFIG_CMD_EXPORTENV=y
|
||||
CONFIG_CMD_IMPORTENV=y
|
||||
CONFIG_CMD_EDITENV=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_ENV_EXISTS=y
|
||||
|
||||
#
|
||||
# Memory commands
|
||||
#
|
||||
CONFIG_CMD_MEMORY=y
|
||||
CONFIG_CMD_CRC32=y
|
||||
# CONFIG_LOOPW is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_MX_CYCLIC is not set
|
||||
# CONFIG_CMD_MEMINFO is not set
|
||||
|
||||
#
|
||||
# Device access commands
|
||||
#
|
||||
|
||||
CONFIG_CMD_DM=y
|
||||
# CONFIG_CMD_DEMO is not set
|
||||
CONFIG_CMD_LOADB=y
|
||||
CONFIG_CMD_LOADS=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
# CONFIG_CMD_NAND is not set
|
||||
# CONFIG_CMD_SF is not set
|
||||
# CONFIG_CMD_SPI is not set
|
||||
# CONFIG_CMD_I2C is not set
|
||||
# CONFIG_CMD_USB is not set
|
||||
CONFIG_CMD_FPGA=y
|
||||
|
||||
#
|
||||
# Shell scripting commands
|
||||
#
|
||||
CONFIG_CMD_ECHO=y
|
||||
CONFIG_CMD_ITEST=y
|
||||
CONFIG_CMD_SOURCE=y
|
||||
CONFIG_CMD_SETEXPR=y
|
||||
|
||||
#
|
||||
# Network commands
|
||||
#
|
||||
|
||||
#
|
||||
# Network PHY
|
||||
#
|
||||
CONFIG_QCA8081_PHY=y
|
||||
|
||||
CONFIG_CMD_NET=y
|
||||
# CONFIG_CMD_TFTPPUT is not set
|
||||
# CONFIG_CMD_TFTPSRV is not set
|
||||
# CONFIG_CMD_RARP is not set
|
||||
# CONFIG_CMD_DHCP is not set
|
||||
CONFIG_CMD_NFS=y
|
||||
# CONFIG_CMD_PING is not set
|
||||
# CONFIG_CMD_CDP is not set
|
||||
# CONFIG_CMD_SNTP is not set
|
||||
# CONFIG_CMD_DNS is not set
|
||||
# CONFIG_CMD_LINK_LOCAL is not set
|
||||
|
||||
#
|
||||
# Misc commands
|
||||
#
|
||||
# CONFIG_CMD_TIME is not set
|
||||
CONFIG_CMD_MISC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_PARTITION_UUIDS=y
|
||||
# CONFIG_CMD_TIMER is not set
|
||||
CONFIG_IPQ_TZT=y
|
||||
CONFIG_UBI_WRITE=y
|
||||
#
|
||||
# Boot timing
|
||||
#
|
||||
# CONFIG_BOOTSTAGE is not set
|
||||
CONFIG_BOOTSTAGE_USER_COUNT=20
|
||||
CONFIG_BOOTSTAGE_STASH_ADDR=0
|
||||
CONFIG_BOOTSTAGE_STASH_SIZE=4096
|
||||
|
||||
#
|
||||
# Power commands
|
||||
#
|
||||
|
||||
#
|
||||
# Security commands
|
||||
#
|
||||
CONFIG_SUPPORT_OF_CONTROL=y
|
||||
|
||||
#
|
||||
# Device Tree Control
|
||||
#
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_BOARD_FIXUP=y
|
||||
CONFIG_OF_SEPARATE=y
|
||||
# CONFIG_OF_EMBED is not set
|
||||
CONFIG_NET=y
|
||||
# CONFIG_NET_RANDOM_ETHADDR is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_DM=y
|
||||
CONFIG_DM_WARN=y
|
||||
CONFIG_DM_DEVICE_REMOVE=y
|
||||
CONFIG_DM_STDIO=y
|
||||
CONFIG_DM_SEQ_ALIAS=y
|
||||
# CONFIG_REGMAP is not set
|
||||
# CONFIG_DEVRES is not set
|
||||
CONFIG_SIMPLE_BUS=y
|
||||
# CONFIG_CLK is not set
|
||||
# CONFIG_CPU is not set
|
||||
|
||||
#
|
||||
# Hardware crypto devices
|
||||
#
|
||||
# CONFIG_FSL_CAAM is not set
|
||||
|
||||
#
|
||||
# Demo for driver model
|
||||
#
|
||||
# CONFIG_DM_DEMO is not set
|
||||
|
||||
#
|
||||
# DFU support
|
||||
#
|
||||
# CONFIG_DFU_TFTP is not set
|
||||
|
||||
#
|
||||
# GPIO Support
|
||||
#
|
||||
# CONFIG_LPC32XX_GPIO is not set
|
||||
# CONFIG_VYBRID_GPIO is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
# CONFIG_DM_I2C_COMPAT is not set
|
||||
# CONFIG_CROS_EC_KEYB is not set
|
||||
|
||||
#
|
||||
# LED Support
|
||||
#
|
||||
# CONFIG_LED is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_CROS_EC is not set
|
||||
# CONFIG_FSL_SEC_MON is not set
|
||||
# CONFIG_PCA9551_LED is not set
|
||||
# CONFIG_RESET is not set
|
||||
|
||||
#
|
||||
# MMC Host controller Support
|
||||
#
|
||||
# CONFIG_DM_MMC is not set
|
||||
CONFIG_MMC_FLASH=y
|
||||
|
||||
#
|
||||
# NAND Device Support
|
||||
#
|
||||
# CONFIG_NAND_DENALI is not set
|
||||
# CONFIG_NAND_VF610_NFC is not set
|
||||
# CONFIG_NAND_PXA3XX is not set
|
||||
|
||||
#
|
||||
# Generic NAND options
|
||||
#
|
||||
# CONFIG_NAND_FLASH is not set
|
||||
|
||||
#
|
||||
# Serial NAND
|
||||
#
|
||||
# CONFIG_QPIC_SERIAL is not set
|
||||
|
||||
#
|
||||
# SPI Flash Support
|
||||
|
||||
#
|
||||
# CONFIG_SPI_FLASH is not set
|
||||
# CONFIG_DM_ETH is not set
|
||||
# CONFIG_PHYLIB is not set
|
||||
# CONFIG_NETDEVICES is not set
|
||||
# CONFIG_IPQ_MTD_NOR is not set
|
||||
# CONFIG_IPQ_TINY_SPI_NOR is not set
|
||||
|
||||
#
|
||||
# PCI
|
||||
#
|
||||
# CONFIG_DM_PCI is not set
|
||||
# CONFIG_PCI_IPQ is not set
|
||||
|
||||
#
|
||||
# Pin controllers
|
||||
#
|
||||
# CONFIG_PINCTRL is not set
|
||||
|
||||
#
|
||||
# Power
|
||||
#
|
||||
# CONFIG_DM_PMIC is not set
|
||||
# CONFIG_DM_REGULATOR is not set
|
||||
# CONFIG_RAM is not set
|
||||
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_DM_RTC is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
CONFIG_REQUIRE_SERIAL_CONSOLE=y
|
||||
# CONFIG_DEBUG_UART is not set
|
||||
|
||||
#
|
||||
|
||||
# Sound support
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# SPI Support
|
||||
#
|
||||
# CONFIG_FSL_ESPI is not set
|
||||
# CONFIG_TI_QSPI is not set
|
||||
# CONFIG_DM_THERMAL is not set
|
||||
|
||||
#
|
||||
# TPM support
|
||||
#
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
# CONFIG_USB is not set
|
||||
# CONFIG_DM_USB is not set
|
||||
# CONFIG_USB_XHCI_IPQ is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_VIDEO_VESA is not set
|
||||
# CONFIG_VIDEO_LCD_ANX9804 is not set
|
||||
# CONFIG_VIDEO_LCD_SSD2828 is not set
|
||||
# CONFIG_DISPLAY_PORT is not set
|
||||
# CONFIG_VIDEO_TEGRA124 is not set
|
||||
# CONFIG_VIDEO_BRIDGE is not set
|
||||
# CONFIG_PHYS_TO_BUS is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
|
||||
#
|
||||
# Library routines
|
||||
|
||||
#
|
||||
# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
|
||||
CONFIG_HAVE_PRIVATE_LIBGCC=y
|
||||
CONFIG_USE_PRIVATE_LIBGCC=y
|
||||
CONFIG_SYS_HZ=1000
|
||||
# CONFIG_SYS_VSNPRINTF is not set
|
||||
CONFIG_REGEX=y
|
||||
# CONFIG_LIB_RAND is not set
|
||||
# CONFIG_CMD_DHRYSTONE is not set
|
||||
# CONFIG_RSA is not set
|
||||
# CONFIG_TPM is not set
|
||||
|
||||
#
|
||||
# Hashing Support
|
||||
#
|
||||
# CONFIG_SHA1 is not set
|
||||
# CONFIG_SHA256 is not set
|
||||
# CONFIG_SHA_HW_ACCEL is not set
|
||||
|
||||
#
|
||||
# Compression Support
|
||||
#
|
||||
# CONFIG_LZ4 is not set
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_ERRNO_STR is not set
|
||||
# CONFIG_UNIT_TEST is not set
|
||||
|
||||
# CONFIG_SYS_THUMB_BUILD is not set
|
||||
# CONFIG_HAS_THUMB2 is not set
|
||||
|
|
@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_IPQ807x) += ipq_gpio.o
|
|||
obj-$(CONFIG_ARCH_IPQ806x) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_IPQ40xx) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_IPQ5018) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_DEVSOC) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_IPQ6018) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_IPQ9574) += ipq_gpio.o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_IPQ807x) += qca_uart.o
|
|||
obj-$(CONFIG_ARCH_IPQ806x) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_IPQ40xx) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_IPQ5018) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_DEVSOC) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_IPQ6018) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_IPQ9574) += qca_uart.o
|
||||
ifdef CONFIG_DM_SERIAL
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi_bam.o
|
|||
obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi_bam.o
|
||||
obj-$(CONFIG_ARCH_IPQ6018) += qca_qup_spi_bam.o
|
||||
obj-$(CONFIG_ARCH_IPQ5018) += qca_qup_spi_bam.o
|
||||
obj-$(CONFIG_ARCH_DEVSOC) += qca_qup_spi_bam.o
|
||||
obj-$(CONFIG_ARCH_IPQ9574) += qca_qup_spi_bam.o
|
||||
|
||||
obj-$(CONFIG_ARCH_IPQ806x) += ipq_spi.o
|
||||
|
|
|
|||
|
|
@ -38,6 +38,9 @@ typedef volatile unsigned char vu_char;
|
|||
#elif defined(CONFIG_IPQ5018)
|
||||
#include <../board/qca/arm/ipq5018/ipq5018.h>
|
||||
|
||||
#elif defined(CONFIG_DEVSOC)
|
||||
#include <../board/qca/arm/devsoc/devsoc.h>
|
||||
|
||||
#elif defined(CONFIG_IPQ6018)
|
||||
#include <../board/qca/arm/ipq6018/ipq6018.h>
|
||||
|
||||
|
|
@ -416,7 +419,10 @@ ulong getenv_hex(const char *varname, ulong default_val);
|
|||
* Return -1 if variable does not exist (default to true)
|
||||
*/
|
||||
int getenv_yesno(const char *var);
|
||||
#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || defined(CONFIG_IPQ806X_ENV) || defined(CONFIG_IPQ5018_ENV) || defined(CONFIG_IPQ6018_ENV) || defined(CONFIG_IPQ9574_ENV)
|
||||
#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || \
|
||||
defined(CONFIG_IPQ806X_ENV) || defined(CONFIG_IPQ5018_ENV) || \
|
||||
defined(CONFIG_DEVSOC_ENV) || defined(CONFIG_IPQ6018_ENV) || \
|
||||
defined(CONFIG_IPQ9574_ENV)
|
||||
extern int (*saveenv)(void);
|
||||
#else
|
||||
int saveenv (void);
|
||||
|
|
|
|||
242
include/configs/devsoc.h
Normal file
242
include/configs/devsoc.h
Normal file
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DEVSOC_H
|
||||
#define _DEVSOC_H
|
||||
|
||||
#ifndef DO_DEPS_ONLY
|
||||
#include <generated/asm-offsets.h>
|
||||
#endif
|
||||
|
||||
#define CONFIG_DEVSOC
|
||||
#undef CONFIG_QCA_DISABLE_SCM
|
||||
#define CONFIG_SPI_FLASH_CYPRESS
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_IPQ_NO_RELOC
|
||||
|
||||
#define CONFIG_SYS_VSNPRINTF
|
||||
|
||||
/*
|
||||
* Enable Early and Late init
|
||||
* This config needs for secondary boot and to set BADOFF5E
|
||||
* This config also need for spi-nor boot,
|
||||
* set size and offset of hlos and rootfs
|
||||
*/
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_DEVSOC_UART
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN 0x4000000
|
||||
|
||||
#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
|
||||
|
||||
/*
|
||||
* This config should remove once
|
||||
* flash support is added
|
||||
*/
|
||||
#define CONFIG_ENV_IS_NOWHERE 1
|
||||
|
||||
/*
|
||||
* Enable Flashwrite command
|
||||
*/
|
||||
#define CONFIG_CMD_FLASHWRITE
|
||||
|
||||
/*
|
||||
* Enable Env overwrite support
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */
|
||||
/*
|
||||
|
||||
svc_sp --> --------------
|
||||
irq_sp --> | |
|
||||
fiq_sp --> | |
|
||||
bd --> | |
|
||||
gd --> | |
|
||||
pgt --> | |
|
||||
malloc --> | |
|
||||
text_base --> |------------|
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\
|
||||
CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\
|
||||
GENERATED_BD_INFO_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#define TLMM_BASE 0x01000000
|
||||
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000)
|
||||
#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x4A400000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
|
||||
|
||||
#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE
|
||||
#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
|
||||
|
||||
#define CONFIG_OF_COMBINE 1
|
||||
|
||||
#define CONFIG_SMEM_VERSION_C
|
||||
#define CONFIG_QCA_SMEM_BASE 0x4AA00000
|
||||
|
||||
#define CONFIG_IPQ_FDT_HIGH 0x48500000
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
|
||||
#define CONFIG_QCA_UBOOT_OFFSET 0xA100000
|
||||
#define CONFIG_UBOOT_END_ADDR 0x4A500000
|
||||
|
||||
/*
|
||||
* IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region.
|
||||
* CONFIG_TZ_END_ADDR: Ending address of Trust Zone and starting
|
||||
* address of WLAN Area.
|
||||
* TFTP file can only be written in Linux HLOS region and WLAN AREA.
|
||||
*/
|
||||
#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20))
|
||||
#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21))
|
||||
#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <compiler.h>
|
||||
extern loff_t board_env_offset;
|
||||
extern loff_t board_env_range;
|
||||
extern loff_t board_env_size;
|
||||
#endif
|
||||
|
||||
#define CONFIG_DEVSOC_ENV 1
|
||||
#define CONFIG_ENV_OFFSET board_env_offset
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
|
||||
#define CONFIG_ENV_RANGE board_env_range
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (500 << 10))
|
||||
|
||||
/*
|
||||
* NAND Flash Configs
|
||||
*/
|
||||
|
||||
/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode
|
||||
* CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode.
|
||||
* BAM is enabled by default.
|
||||
*/
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
|
||||
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define CONFIG_IPQ_NO_MACS 1
|
||||
|
||||
/*
|
||||
* Block Device & Disk Partition Config
|
||||
*/
|
||||
#define HAVE_BLOCK_DEVICE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* Expose SPI driver as a pseudo NAND driver to make use
|
||||
* of U-Boot's MTD framework.
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \
|
||||
CONFIG_IPQ_MAX_SPI_DEVICE
|
||||
|
||||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
|
||||
|
||||
#define CONFIG_IPQ_MAX_BLSP_QUPS 3
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
|
||||
|
||||
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
|
||||
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
|
||||
|
||||
#define QCA_SPI_NOR_DEVICE "spi0.0"
|
||||
|
||||
/*
|
||||
* U-Boot Env Configs
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_CMD_XIMG
|
||||
|
||||
/* MTEST */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x1300000
|
||||
#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + 0x100
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootipq"
|
||||
#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
|
||||
#define QCA_ROOT_FS_PART_NAME "rootfs"
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
#define NUM_ALT_PARTITION 16
|
||||
|
||||
#undef CONFIG_GZIP
|
||||
#undef CONFIG_ZLIB
|
||||
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
|
||||
/* Mii command support */
|
||||
#define CONFIG_CMD_MII
|
||||
|
||||
/*
|
||||
* Below Configs need to be updated after enabling reset_crashdump
|
||||
* Included now to avoid build failure
|
||||
*/
|
||||
|
||||
#define DLOAD_DISABLE 0x1
|
||||
#define SET_MAGIC 0x1
|
||||
#define CLEAR_MAGIC 0x0
|
||||
#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
|
||||
#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
|
||||
#define SCM_CMD_TZ_PSHOLD 0x16
|
||||
#define BOOT_VERSION 0
|
||||
#define TZ_VERSION 1
|
||||
|
||||
|
||||
#define CONFIG_DEVSOC_TZ_WONCE_4_ADDR 0x193d010
|
||||
|
||||
/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
|
||||
* Cache flush and invalidation based on L1 cache, so the cache line
|
||||
* size is configured to 64 */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
#undef CONFIG_BOOTM_PLAN9
|
||||
#undef CONFIG_BOOTM_RTEMS
|
||||
#undef CONFIG_BOOTM_VXWORKS
|
||||
|
||||
#endif /* _DEVSOC_H */
|
||||
62
include/dt-bindings/qcom/gpio-devsoc.h
Normal file
62
include/dt-bindings/qcom/gpio-devsoc.h
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_DEVSOC_GPIO_H__
|
||||
#define __DT_BINDINGS_DEVSOC_GPIO_H__
|
||||
|
||||
/* GPIO TLMM: Direction */
|
||||
#define GPIO_INPUT 0
|
||||
#define GPIO_OUTPUT 1
|
||||
|
||||
/* GPIO TLMM: Output value */
|
||||
#define GPIO_OUT_LOW 0
|
||||
#define GPIO_OUT_HIGH 1
|
||||
|
||||
/* GPIO TLMM: Pullup/Pulldown */
|
||||
#define GPIO_NO_PULL 0
|
||||
#define GPIO_PULL_DOWN 1
|
||||
#define GPIO_KEEPER 2
|
||||
#define GPIO_PULL_UP 3
|
||||
|
||||
/* GPIO TLMM: Drive Strength */
|
||||
#define GPIO_2MA 0
|
||||
#define GPIO_4MA 1
|
||||
#define GPIO_6MA 2
|
||||
#define GPIO_8MA 3
|
||||
#define GPIO_10MA 4
|
||||
#define GPIO_12MA 5
|
||||
#define GPIO_14MA 6
|
||||
#define GPIO_16MA 7
|
||||
|
||||
/* GPIO TLMM: Status */
|
||||
#define GPIO_OE_DISABLE 0
|
||||
#define GPIO_OE_ENABLE 1
|
||||
|
||||
/* GPIO OD */
|
||||
#define GPIO_OD_ENABLE 1
|
||||
#define GPIO_OD_DISABLE 0
|
||||
|
||||
/* GPIO SR */
|
||||
#define GPIO_SR_ENABLE 1
|
||||
#define GPIO_SR_DISABLE 0
|
||||
|
||||
/* GPIO PULLUP RES */
|
||||
#define GPIO_PULL_RES0 0
|
||||
#define GPIO_PULL_RES1 1
|
||||
#define GPIO_PULL_RES2 2
|
||||
#define GPIO_PULL_RES3 3
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Add table
Reference in a new issue