This patch enables qca8x8x switch support on ipq6018.
Change-Id: I5e037071dad112558682255f99bac2adb2b411b5
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This changes clean and disable edma before
jumping to kernel.
Change-Id: I324a9b410fb94e1e01e63ad77c46b5129bc76e54
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This patch skips uniphy configuration if it is already
configured with the requested mode.
Change-Id: I4aa1f249a5393881f83e35f3016259986085921c
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
during recovery mode dcache will not be available.
So, skip dcache disable and enable during
network transfer
Change-Id: Icc89c846580ebcd73332061a55ae9d8c15fa2b1a
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
Changing the data type of phy_chip_id1 and phy_chip_id2 from
32-bit to 16-bit and initializing them to 0 to avoid any junk
value while shifting and concatenating them to form the final
phy_chip_id.
Change-Id: If96b01db9ec2b3c0a259ea3c98516d1f18a898ce
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
update the port clock setting for qca8084 PHY with respect to
10M speed configuration.
Change-Id: I16403b155f31f37a6bdf828150ca2d0923a29f3e
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Previously 100M speed is not working in port 4 of MHT
by-pass mode. SGMII speed fixup required to dynamically
adjust the gcc clock based on the link-speed.
Still, this is requried only for port 4, because remaining
ports (1-3) will be taken care from switch core. So, added
speed fix for the by-mode support.
Change-Id: I495aad4b64de12ae7f57c0bdb9e0def08ad38681
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This changes updates the gcc common clk initialise
steps and adds support for obtaining bitmap
details from dts.
Change-Id: I55e895989823a4fbb97c638ad937ca48c00519c5
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change set SGMII mode and force mode based on
dts entries.
Change-Id: Ideaa1bb77fe8fb37a7e6b907a987f6dcac54917f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes enable both PHY and switch configure
simultaneously and also switch can be configure
to any port.
And also these changes enable dual MDIO bus support.
Change-Id: Ib86c8a15abb9a7a35aa86d87cef78ad917dd1a00
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Added new config called CONFIG_QCA8084_BYPASS_MODE and moved
all the qca8084 by-pass mode related code under it.
Change-Id: I4157960989cd67576803d494594869265fc81745
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Added QCA8084 by-pass mode support on MI01.1 RDP
Change-Id: I1a14729cac5463675f9cb0d15df3da76746aa81e
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
These changes update config as like below.
1.Config 100M, 1G as GMAC, 2.5G as XGMAC
2.Config MHT as XGMAC.
Change-Id: I0566f3a3d364931e8c8173c3604160f24c2439be
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes includes update the Speed clock,
common clock update and dts nodes.
Change-Id: I673e8ccf191048fef966a8f6cd84858e1a3b824f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Only one SFP port can be enabled at time with
either SGMII or SGMII PLUS mode.
Mode shall be specified from dts for 1G or 2.5G
support respectively. Add below change to enable
SFP as this change is not mainlined.
gmac_cfg {
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
- phy_address = <0x1c>;
- napa_gpio = <39>;
/*
* 6 - SGMII_PLUS (2.5G),
* 8 - SGMII_FIBER (1G)
*/
+ switch_mac_mode = <8>;
+ sfp_tx_gpio = <27>;
+ sfp_rx_gpio = <29>;
};
};
Change-Id: I507be2b84b1f932802659abffa3288e304e0d411
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
This change adds usxgmii support in UNIPHY0.
Earlier it was supported up to PSGMII with 4 ports.
With these changes,
UNIPHY0 supports either of the 2 modes mentioned below.
1. PSGMII with 4 ports
2. USXGMII with 1 port
Change-Id: Ic4ca62e3ef74d275cda92d86b459d204ee4325ed
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
During long run tests on image download in u-boot,
EDMA crash was observed as the SKB buffer address
returned by the RX descriptor was corrupted and was
pointing to an invalid address:
clean_rx: p: 14 c: 0 skb: 61763b10
WARN: src_info_type:0x0. Drop skb:61763b10
The reason for corruption seems to be the RX buffer allocation that was
happening twice before initiating the EDMA for the next transaction.
This change removes the additional allocation of the Rx buffer which is
not needed.
Change-Id: I4a5b404527469ff3b981749aa4e05080f55807cd
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
During long run tests on image download in u-boot,
EDMA crash was observed as the SKB buffer address
returned by the RX descriptor was corrupted and was
pointing to an invalid address:
clean_rx: p: 14 c: 0 skb: 61763b10
WARN: src_info_type:0x0. Drop skb:61763b10
The reason for corruption seems to be the RX buffer allocation that was
happening twice before initiating the EDMA for the next transaction.
This change removes the additional allocation of the Rx buffer which is
not needed.
Change-Id: I919024df8131fe87640ecc0d481b61012742efbf
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
