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drivers: net: skip configuration if already configured
This patch skips uniphy configuration if it is already configured with the requested mode. Change-Id: I4aa1f249a5393881f83e35f3016259986085921c Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
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parent
065478fcfd
commit
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6 changed files with 24 additions and 3 deletions
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@ -36,6 +36,7 @@ extern int ipq_mdio_write(int mii_id,
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extern int ipq_mdio_read(int mii_id,
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int regnum, ushort *data);
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extern void ipq5332_qca8075_phy_serdes_reset(u32 phy_id);
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int uniphy_cur_mode[PPE_MAX_UNIPHY_INSTANCE] = {-1, -1};
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void csr1_write(int phy_id, int addr, int value)
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{
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@ -411,6 +412,9 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
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void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
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{
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if (uniphy_cur_mode[uniphy_index] == mode)
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return;
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switch(mode) {
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case EPORT_WRAPPER_PSGMII:
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ppe_uniphy_psgmii_mode_set(uniphy_index);
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@ -432,8 +436,10 @@ void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
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ppe_uniphy_10g_r_mode_set(uniphy_index);
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break;
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default:
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break;
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return;
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}
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uniphy_cur_mode[uniphy_index] = mode;
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}
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void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index)
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@ -16,6 +16,7 @@
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#define PPE_UNIPHY_INSTANCE0 0
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#define PPE_UNIPHY_INSTANCE1 1
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#define PPE_MAX_UNIPHY_INSTANCE 2
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#define GCC_UNIPHY_REG_INC 0x10
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#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0
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@ -29,6 +29,7 @@ extern int ipq_mdio_write(int mii_id,
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extern int ipq_mdio_read(int mii_id,
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int regnum, ushort *data);
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extern void qca8075_phy_serdes_reset(u32 phy_id);
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int uniphy_cur_mode[PPE_MAX_UNIPHY_INSTANCE] = {-1, -1};
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void csr1_write(int phy_id, int addr, int value)
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{
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@ -257,6 +258,9 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
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void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
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{
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if (uniphy_cur_mode[uniphy_index] == mode)
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return;
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switch(mode) {
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case PORT_WRAPPER_PSGMII:
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ppe_uniphy_psgmii_mode_set(uniphy_index);
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@ -278,8 +282,10 @@ void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
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ppe_uniphy_10g_r_mode_set(uniphy_index);
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break;
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default:
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break;
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return;
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}
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uniphy_cur_mode[uniphy_index] = mode;
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}
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void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index)
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@ -14,6 +14,7 @@
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#define PPE_UNIPHY_INSTANCE0 0
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#define PPE_UNIPHY_INSTANCE1 1
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#define PPE_MAX_UNIPHY_INSTANCE 2
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#define GCC_UNIPHY1_PORT5_RX_CBCR 0x1856110
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#define GCC_UNIPHY1_PORT5_TX_CBCR 0x1856114
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#define GCC_NSS_PORT5_RX_CBCR 0x1868260
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@ -38,6 +38,7 @@ extern int ipq_mdio_read(int mii_id,
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int regnum, ushort *data);
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extern void ipq9574_qca8075_phy_serdes_reset(u32 phy_id);
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extern void qca8084_phy_interface_mode_set(void);
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int uniphy_cur_mode[PPE_MAX_UNIPHY_INSTANCE] = {-1, -1, -1};
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void csr1_write(int phy_id, int addr, int value)
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{
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@ -636,6 +637,9 @@ void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
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return;
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}
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if (uniphy_cur_mode[uniphy_index] == mode)
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return;
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switch(mode) {
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case EPORT_WRAPPER_PSGMII:
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ppe_uniphy_psgmii_mode_set(uniphy_index);
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@ -661,8 +665,10 @@ void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
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ppe_uniphy_uqxgmii_mode_set(uniphy_index);
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break;
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default:
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break;
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return;
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}
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uniphy_cur_mode[uniphy_index] = mode;
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}
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void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index)
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@ -15,6 +15,7 @@
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#define PPE_UNIPHY_INSTANCE1 1
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#define PPE_UNIPHY_INSTANCE2 2
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#define PPE_MAX_UNIPHY_INSTANCE 3
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#define GCC_UNIPHY_REG_INC 0x10
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#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0
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