This patch does minor code reorganization to store spare, ecc and
bbm bytes in nand device structure which will be useful in
subsequent patches.
Change-Id: Id44c53e204a874569968764798c346a609695acf
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation for
checking the read errors
1. For checking the erased CW, NAND_ERASED_CW_DETECT_STATUS
is being read inside qpic_nand_check_status. The
qpic_nand_check_status will be called after complete page read
so reading status register won’t help in getting the register
value after each CW reads.
2. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
3. mtd->ecc_stats is only applicable when ECC engine is
doing ECC correction. For raw reads, the stats should not be
incremented.
Now the changes have been done to reorganize the error handling
1. schedule the NAND_ERASED_CW_DETECT_STATUS reading after
every CW read and check the same if ECC engine generates
uncorrectable error.
2. For raw read, the ECC engine will never generate the
uncorrectable error or erased CW so check only
NAND_FLASH_STATUS.
3. The qpic_nand_read_oob should return the maximum number
of bitflips that were corrected on any one ecc region so
introduce the max_bitflips for maintaining the same.
4. The read should return the complete data in case of
BADMSG so move the BADMSG check in the main read function.
Change-Id: Ibef56294ace00d7cd67b501f623fb1d3aeb2c6ec
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. ecc strength can be assigned in mtd structure itself so
remove the ecc_width from qpic nand dev structure
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: Ieafd1957b89a05f9dd0fdfe829712d8891bd6a48
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
NANDC_RESULT_BAD_PAGE is not being returned by any operation, so
it can be removed.
Change-Id: Ia90e4e6b7ef7577d069d312d51083b50f49bf980
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
This patch enables SDHCI mode and also supports
data transfer using ADMA method.
Change-Id: Ia3187fec9024ad0972ca720cf0b9ddc6a59b906c
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
Reset command must be the first command issued to all
targets after the NAND flash device is powered on.
Change-Id: I617dc5b0ad8d72705dcf20f1cb554134b166e533
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
MDIO clock divider is set to 0x7 (counts to 8)
to produce 12.5MHz (100MHz/8) MDC frequency.
Change-Id: Ic7969aebf9fcbb14601ba8e56563959ab0b25657
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
The EDMA HW is unable to process packets less than MIN_PKT_SIZE(33) bytes,
then the EDMA stalls. This is to pad the packets up to MIN_PKT_SIZE.
Change-Id: I473831a759ad6a764fefa095cf7ab347ba95ee97
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
ipq40xx, ipq807x hardware share the qca8033 phy. So the qca8033 phy
driver has been moved to common directory for use by both the
hardware.
Change-Id: Ic972f00770c9e3cbaf4d727df21f19cd926ddce2
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This patch added the uniphy interface mode and port mux select
for PSGMII and SGMII.
Change-Id: I26f18a855b9972a358583d706d3f8a8bf09401cc
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
The UBI layer generates the following data aborts if any of the
NAND block contains bit flips
ubi0: attaching mtd2
ubi0: fixable bit-flip detected at PEB 149
ubi0: scanning is finished
ubi0: fixable bit-flip detected at PEB 149
data abort
pc : [<4a934cc8>] lr : [<4a933aec>]
reloc pc : [<4a934cc8>] lr : [<4a933aec>]
sp : 4a77f2e0 ip : 00000095 fp : 00000075
r10: 000001b7 r9 : 4a77fea0 r8 : 00000001
r7 : 0001f000 r6 : 0001f000 r5 : 4a785e40 r4 : 4a7c4180
r3 : 00000000 r2 : 00000075 r1 : 4a7860b8 r0 : 4a7c49c0
Flags: nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
UBI layer will move the data from original block to some other
block in case of bit flips in the function ubi_eba_copy_leb. This
function uses volume EBA table vol->eba_tbl. The current UBI code
calls ubi_wl_init followed by ubi_eba_init but the ubi_eba_init
only initializes the volume EBA table. In case of bit failure,
the ubi_wl_init calls function __schedule_ubi_work which will
call ubi_eba_copy_leb and triggers data abort.
ubi_attach() {
ubi_wl_init -> __schedule_ubi_work -> ubi_eba_copy_leb
ubi_eba_init
}
The UBI code has been written for Linux kernel and it has been
ported to UBOOT. Since UBOOT does not support threads so all the
thread functions are being called in uboot synchronously.
In Linux kernel, the UBI background thread starts
after the initialization, which is being controlled by
thread_enabled variable which will be set to true after all
initialization.
Now this patch checks for thread_enabled variable and call the
do_work only if the thread is enabled.
Change-Id: I4b2b40031dbd5f16ceefef541248973ca326cd9c
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
NAND_CMD_PRG_PAGE_ALL uses the spare data from buffer itself
which is not applicable. The spare area in NAND page for
QPIC are dummy bytes so 0xff should be written to these
spare area. NAND_CMD_PRG_PAGE does the same thing and HLOS
driver uses this command for all page program
operations. The actual spare data is being written along
with every codeword since the codewords size is 516 in which
512 bytes are user data and 4 bytes are spare data.
Change-Id: I5651caf5ea95f046570e8318f59e140398869ece
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. This driver is directly being registered with MTD
layer so for OOB operations, the device OOB size will be
passed. QPIC can’t handle the complete OOB so calculate QPIC
supported OOB size and overwrite the device OOB size with
QPIC supported OOB size.
2. OOB available calculation was wrong. The available OOB’s are
4 bytes per codeword.
3. Raw configuration codeword size was hardcoded to 528 while 8
bit ECC codeword size is 532.
Change-Id: Idc118e2fdd9882758da9dc6b1e977e04697a5640
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
The QPIC XFER STEPS will not be configured in non NAND boot
mode and the data transfer speed will be very slow. Now this
patch reads the timing parameter from ONFI page and configures
the NAND XFER STEPS registers for highest supported ONFI mode.
For NON ONFI device, it will configure to default mode.
Change-Id: I2daf4a92255307efc53db9bb7fe2f02e8c00c3fa
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Cleared dynamically allocated region for spi global data
to avoid garbage values causing data abort.
Change-Id: Ie278cb3a1374d347d7dfb20b59059dfbf9a7ae42
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
If the PCIE cards are not connected, executing the pci
commands lead to the crash.
Change-Id: Id68ab1a39bfc3319d17af2fe6a3c8d4c1af039b0
Signed-off-by: smuthayy <smuthayy@codeaurora.org>
ipq40xx, ipq807x hardware share the qca8075 phy. So the qca8075 phy
mdio, driver has been moved to common directory for use by both the
hardware.
Change-Id: Id6e9342438ffbdf8599860df6fbb39bba30429b3
Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
