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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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IPQ807x: AQ Phy Fw download from flash
Change-Id: I55ecb7ab61476c497ae565597396556e4f074e8e Signed-off-by: Ramesh Muthusamy <rmuthusa@codeaurora.org> Signed-off-by: Saravanan Jaganathan <sjaganat@codeaurora.org>
This commit is contained in:
Ramesh Muthusamy
Gerrit - the friendly Code Review server
parent
b22b421ccf
commit
040da09949
3 changed files with 157 additions and 34 deletions
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@ -251,9 +251,8 @@ void board_mmc_deinit(void)
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emmc_clock_disable();
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}
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int board_eth_init(bd_t *bis)
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void eth_clock_enable(void)
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{
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int ret=0;
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int tlmm_base = 0x1025000;
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int aquantia_gpio = -1, node;
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unsigned int *aquantia_gpio_base;
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@ -329,6 +328,13 @@ int board_eth_init(bd_t *bis)
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writel(0x3, aquantia_gpio_base);
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mdelay(500);
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}
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}
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int board_eth_init(bd_t *bis)
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{
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int ret=0;
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eth_clock_enable();
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ret = ipq807x_edma_init(NULL);
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if (ret != 0)
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@ -21,12 +21,44 @@
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#include "ipq_phy.h"
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#include "ipq807x_aquantia_phy.h"
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#include <crc.h>
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#include <mmc.h>
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#include <asm/errno.h>
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#include <nand.h>
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#include <spi_flash.h>
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#include <spi.h>
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typedef struct {
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unsigned int image_type;
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unsigned int header_vsn_num;
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unsigned int image_src;
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unsigned char *image_dest_ptr;
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unsigned int image_size;
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unsigned int code_size;
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unsigned char *signature_ptr;
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unsigned int signature_size;
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unsigned char *cert_chain_ptr;
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unsigned int cert_chain_size;
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} mbn_header_t;
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mbn_header_t *fwimg_header;
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static int debug = 0;
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#ifdef CONFIG_QCA_MMC
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extern qca_mmc mmc_host;
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static qca_mmc *host = &mmc_host;
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#endif
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extern int ipq_mdio_write(int mii_id,
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int regnum, u16 value);
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extern int ipq_mdio_read(int mii_id,
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int regnum, ushort *data);
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extern int ipq_sw_mdio_init(const char *);
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extern void eth_clock_enable(void);
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static int program_ethphy_fw(unsigned int phy_addr,
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uint32_t load_addr,uint32_t file_size );
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static qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
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u16 aq_phy_reg_write(u32 dev_id, u32 phy_id,
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u32 reg_id, u16 reg_val)
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{
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@ -167,13 +199,116 @@ int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id)
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return 0;
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}
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#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300
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static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int phy_addr=0x7;
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if (argc > 2)
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return CMD_RET_USAGE;
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if (argc == 2)
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phy_addr = simple_strtoul(argv[1], NULL, 16);
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if (phy_addr != AQU_PHY_ADDR) {
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printf("Phy address is not correct: use 0x7\n");
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return 0;
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}
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miiphy_init();
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eth_clock_enable();
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ipq_sw_mdio_init("IPQ MDIO0");
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ipq_board_fw_download(phy_addr);
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return 0;
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}
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int ipq_board_fw_download(unsigned int phy_addr)
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{
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char runcmd[256];
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int ret,i=0;
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uint32_t start; /* block number */
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uint32_t size; /* no. of blocks */
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qca_part_entry_t ethphyfw;
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struct { char *name; qca_part_entry_t *part; } entries[] = {
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{ "0:ETHPHYFW", ðphyfw },
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};
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#ifdef CONFIG_QCA_MMC
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block_dev_desc_t *blk_dev;
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disk_partition_t disk_info;
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#endif
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/* check the smem info to see which flash used for booting */
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if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) {
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if (debug) {
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printf("Using nand device %d\n", CONFIG_SPI_FLASH_INFO_IDX);
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}
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sprintf(runcmd, "nand device %d", CONFIG_SPI_FLASH_INFO_IDX);
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run_command(runcmd, 0);
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} else if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) {
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if (debug) {
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printf("Using nand device 0\n");
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}
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} else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH) {
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if (debug) {
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printf("Using MMC device\n");
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}
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} else {
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printf("Unsupported BOOT flash type\n");
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return -1;
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}
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ret = smem_getpart(entries[i].name, &start, &size);
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if (ret < 0) {
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debug("cdp: get part failed for %s\n", entries[i].name);
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} else {
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qca_set_part_entry(entries[i].name, sfi, entries[i].part, start, size);
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}
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if ( (sfi->flash_type == SMEM_BOOT_NAND_FLASH) || (sfi->flash_type == SMEM_BOOT_SPI_FLASH)) {
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/*
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* Kernel is in a separate partition
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*/
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snprintf(runcmd, sizeof(runcmd),
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/* NOR is treated as psuedo NAND */
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"nand read 0x%x 0x%llx 0x%llx && ",
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CONFIG_SYS_LOAD_ADDR, ethphyfw.offset, ethphyfw.size);
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if (debug)
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printf("%s", runcmd);
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if (run_command(runcmd, 0) != CMD_RET_SUCCESS)
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return CMD_RET_FAILURE;
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#ifdef CONFIG_QCA_MMC
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} else if (sfi->flash_type == SMEM_BOOT_MMC_FLASH ) {
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blk_dev = mmc_get_dev(host->dev_num);
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ret = get_partition_info_efi_by_name(blk_dev,
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"0:ETHPHYFW", &disk_info);
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if (ret == 0) {
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snprintf(runcmd, sizeof(runcmd), "mmc read 0x%x 0x%X 0x%X",
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CONFIG_SYS_LOAD_ADDR,
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(uint)disk_info.start, (uint)disk_info.size);
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if (run_command(runcmd, 0) != CMD_RET_SUCCESS)
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return CMD_RET_FAILURE;
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}
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#endif
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}
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fwimg_header = CONFIG_SYS_LOAD_ADDR;
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if( fwimg_header->image_type == 0x13 && fwimg_header->header_vsn_num == 0x3) {
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program_ethphy_fw(phy_addr, (uint32_t )(CONFIG_SYS_LOAD_ADDR + sizeof(mbn_header_t)),
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(uint32_t )(fwimg_header->image_size));
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}else {
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printf("bad magic on ETHPHYFW partition\n");
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return -1;
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}
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return 0;
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}
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#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300
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static int program_ethphy_fw(unsigned int phy_addr, uint32_t load_addr, uint32_t file_size)
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{
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int i;
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uint32_t load_addr;
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uint32_t file_size;
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unsigned int phy_addr;
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uint8_t *buf;
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uint16_t file_crc;
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uint16_t computed_crc;
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@ -197,24 +332,13 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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uint8_t lsb2;
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uint16_t mailbox_crc;
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if (argc < 4)
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return CMD_RET_USAGE;
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phy_addr = simple_strtoul(argv[1], NULL, 16);
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load_addr = simple_strtoul(argv[2], NULL, 16);
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file_size = simple_strtoul(argv[3], NULL, 16);
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if (phy_addr != AQU_PHY_ADDR) {
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printf("Phy address is not correct: use 0x7\n");
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return 0;
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}
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300), 0xdead);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301), 0xbeaf);
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reg1 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300));
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reg2 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301));
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if(reg1 != 0xdead && reg2 != 0xbeaf) {
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printf("Scratchpad Read/Write test fail\n");
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printf("PHY::Scratchpad Read/Write test fail\n");
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return 0;
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}
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buf = (uint8_t *)load_addr;
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@ -222,10 +346,10 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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computed_crc = cyg_crc16(buf, file_size - 2);
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if (file_crc != computed_crc) {
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printf("CRC check failed on image file\n");
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printf("CRC check failed on phy fw file\n");
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return 0;
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} else {
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printf ("CRC check good on image file (0x%04X)\n",computed_crc);
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printf ("CRC check good on phy fw file (0x%04X)\n",computed_crc);
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}
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daisy_chain_dis = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452));
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@ -255,15 +379,10 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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primary_iram_ptr += primary_header_ptr;
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primary_dram_ptr += primary_header_ptr;
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printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n");
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printf ("Primary Iram Address: 0x%x\n", primary_iram_ptr);
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printf ("Primary Iram Size: 0x%x\n", primary_iram_sz);
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printf ("Primary Dram Address: 0x%x\n", primary_dram_ptr);
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printf ("Primary Dram Size: 0x%x\n", primary_dram_sz);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x1000);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x0);
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computed_crc = 0;
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printf("Loading IRAM\n");
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printf("PHYFW:Loading IRAM...........");
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x4000);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0);
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byte_sz = primary_iram_sz;
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@ -285,8 +404,6 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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if (i && ((i % 512) == 0))
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printf(" Byte: %X:\n", i << 2);
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}
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switch (byte_sz & 0x3) {
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@ -319,7 +436,8 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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}
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printf("Loading DRAM\n");
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printf("done.\n");
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printf("PHYFW:Loading DRAM..............");
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x3ffe);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0);
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byte_sz = primary_dram_sz;
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@ -341,8 +459,6 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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if (i && ((i % 512) == 0))
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printf(" Byte: %X:\n", i << 2);
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}
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switch (byte_sz & 0x3) {
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@ -375,12 +491,13 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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}
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printf("done.\n");
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x2010);
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mailbox_crc = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x201));
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if (mailbox_crc != computed_crc)
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printf("Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", mailbox_crc, computed_crc);
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printf("phy fw image load CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", mailbox_crc, computed_crc);
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else
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printf("Image load good - mailbox CRC-16 matches (0x%X)\n", mailbox_crc);
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printf("phy fw image load good CRC-16 matches (0x%X)\n", mailbox_crc);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x0), 0x0);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41);
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@ -391,7 +508,6 @@ static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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aquantia_phy_restart_autoneg(phy_addr);
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return 0;
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}
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U_BOOT_CMD(
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aq_load_fw, 5, 1, do_load_fw,
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"LOAD aq-fw-binary",
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@ -1726,6 +1726,7 @@ int ipq807x_edma_init(void *edma_board_cfg)
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break;
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case AQUANTIA_PHY_107:
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case AQUANTIA_PHY_109:
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ipq_board_fw_download(phy_addr);
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ipq_qca_aquantia_phy_init(&ipq807x_edma_dev[i]->ops[phy_id], phy_addr);
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break;
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default:
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