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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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ipq807x: Added the Aquantia phy support
Change-Id: I4c61cd57cf02a97b6410ac4488e2dbe6e6a3cfd3 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This commit is contained in:
Sham Muthayyan
Gerrit - the friendly Code Review server
parent
b5a3729df6
commit
546ffbe6c8
5 changed files with 197 additions and 0 deletions
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@ -86,3 +86,4 @@ obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_uniphy.o
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obj-$(CONFIG_IPQ_MDIO) += ipq_common/ipq_mdio.o
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obj-$(CONFIG_QCA8075_PHY) += ipq_common/ipq_qca8075.o
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obj-$(CONFIG_QCA8033_PHY) += ipq_common/ipq_qca8033.o
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obj-$(CONFIG_QCA_AQUANTIA_PHY) += ipq807x/ipq807x_aquantia_phy.o
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148
drivers/net/ipq807x/ipq807x_aquantia_phy.c
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148
drivers/net/ipq807x/ipq807x_aquantia_phy.c
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@ -0,0 +1,148 @@
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <phy.h>
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#include <miiphy.h>
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#include "ipq_phy.h"
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#include "ipq807x_aquantia_phy.h"
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extern int ipq_mdio_write(int mii_id,
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int regnum, u16 value);
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extern int ipq_mdio_read(int mii_id,
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int regnum, ushort *data);
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u16 aq_phy_reg_write(u32 dev_id, u32 phy_id,
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u32 reg_id, u16 reg_val)
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{
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ipq_mdio_write(phy_id, reg_id, reg_val);
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return 0;
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}
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u16 aq_phy_reg_read(u32 dev_id, u32 phy_id, u32 reg_id)
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{
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return ipq_mdio_read(phy_id, reg_id, NULL);
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}
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u8 aq_phy_get_link_status(u32 dev_id, u32 phy_id)
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{
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u16 phy_data;
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uint32_t reg;
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reg = AQ_PHY_AUTO_STATUS_REG | AQUANTIA_MII_ADDR_C45;
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phy_data = aq_phy_reg_read(dev_id, phy_id, reg);
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phy_data = aq_phy_reg_read(dev_id, phy_id, reg);
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if (((phy_data >> 2) & 0x1) & PORT_LINK_UP)
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return 0;
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return 1;
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}
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u32 aq_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex)
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{
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u16 phy_data;
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uint32_t reg;
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reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45;
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phy_data = aq_phy_reg_read(dev_id, phy_id, reg);
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/*
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* Read duplex
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*/
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phy_data = phy_data & 0x1;
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if (phy_data & 0x1)
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*duplex = FAL_FULL_DUPLEX;
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else
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*duplex = FAL_HALF_DUPLEX;
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return 0;
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}
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u32 aq_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed)
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{
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u16 phy_data;
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uint32_t reg;
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reg = AQ_PHY_LINK_STATUS_REG | AQUANTIA_MII_ADDR_C45;
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phy_data = aq_phy_reg_read(dev_id, phy_id, reg);
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switch ((phy_data >> 1) & 0x7) {
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case SPEED_10G:
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*speed = FAL_SPEED_10000;
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break;
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case SPEED_5G:
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*speed = FAL_SPEED_5000;
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break;
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case SPEED_2_5G:
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*speed = FAL_SPEED_2500;
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break;
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case SPEED_1000MBS:
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*speed = FAL_SPEED_1000;
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break;
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case SPEED_100MBS:
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*speed = FAL_SPEED_100;
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break;
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case SPEED_10MBS:
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*speed = FAL_SPEED_10;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id)
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{
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u16 phy_data;
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struct phy_ops *aq_phy_ops;
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aq_phy_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops));
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if (!aq_phy_ops)
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return -ENOMEM;
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aq_phy_ops->phy_get_link_status = aq_phy_get_link_status;
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aq_phy_ops->phy_get_speed = aq_phy_get_speed;
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aq_phy_ops->phy_get_duplex = aq_phy_get_duplex;
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*ops = aq_phy_ops;
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID1));
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printf ("PHY ID1: 0x%x\n", phy_data);
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(1, QCA_PHY_ID2));
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printf ("PHY ID2: 0x%x\n", phy_data);
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS,
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AQUANTIA_PHY_XS_USX_TRANSMIT));
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phy_data |= AQUANTIA_PHY_USX_AUTONEG_ENABLE;
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aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS,
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AQUANTIA_PHY_XS_USX_TRANSMIT), phy_data);
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG,
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AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK));
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phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE;
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aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG,
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AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK), phy_data);
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS,
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AQUANTIA_GLOBAL_INTR_STANDARD_MASK));
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phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK;
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aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS,
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AQUANTIA_GLOBAL_INTR_STANDARD_MASK), phy_data);
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS,
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AQUANTIA_GLOBAL_INTR_VENDOR_MASK));
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phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK;
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aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS,
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AQUANTIA_GLOBAL_INTR_VENDOR_MASK), phy_data);
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return 0;
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}
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45
drivers/net/ipq807x/ipq807x_aquantia_phy.h
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45
drivers/net/ipq807x/ipq807x_aquantia_phy.h
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@ -0,0 +1,45 @@
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define AQUANTIA_MII_ADDR_C45 (1<<30)
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#define AQUANTIA_REG_ADDRESS(dev_ad, reg_num) (AQUANTIA_MII_ADDR_C45 |\
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((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF))
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#define AQUANTIA_MMD_PHY_XS_REGISTERS 4
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#define AQUANTIA_PHY_XS_USX_TRANSMIT 0xc441
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#define AQUANTIA_PHY_USX_AUTONEG_ENABLE 0x8
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#define AQUANTIA_MMD_AUTONEG 0x7
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#define AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK 0xD401
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#define AQUANTIA_INTR_LINK_STATUS_CHANGE 0x0001
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#define AQUANTIA_MMD_GLOABLE_REGISTERS 0x1E
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#define AQUANTIA_GLOBAL_INTR_STANDARD_MASK 0xff00
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#define AQUANTIA_ALL_VENDOR_ALARMS_INTERRUPT_MASK 0x0001
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#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01
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#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001
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#define AQ_PHY_AUTO_STATUS_REG 0x70001
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#define PORT_LINK_DOWN 0
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#define PORT_LINK_UP 1
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#define AQ_PHY_LINK_STATUS_REG 0x7c800
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#define SPEED_5G 5
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#define SPEED_2_5G 4
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#define SPEED_10G 3
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#define SPEED_1000MBS 2
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#define SPEED_100MBS 1
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#define SPEED_10MBS 0
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@ -63,6 +63,8 @@ typedef enum {
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FAL_SPEED_10 = 10,
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FAL_SPEED_100 = 100,
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FAL_SPEED_1000 = 1000,
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FAL_SPEED_2500 = 2500,
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FAL_SPEED_5000 = 5000,
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FAL_SPEED_10000 = 10000,
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FAL_SPEED_BUTT = 0xffff,
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} fal_port_speed_t;
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@ -286,6 +286,7 @@ extern loff_t board_env_size;
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#define CONFIG_IPQ_MDIO 1
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#define CONFIG_QCA8075_PHY 1
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#define CONFIG_QCA8033_PHY 1
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#define CONFIG_QCA_AQUANTIA_PHY 1
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#define CONFIG_IPQ_ETH_INIT_DEFER
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/*
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