This patch enables support for USB 2.0 in AP-MI01.2
Change-Id: I4f848a403f3aae45a9f1cfa136781fbc7a37c35a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The pcie AUX clock source changed to XO as per
GCC frequency plan
Change-Id: If032831d3a9523ec214a62cbed2950ee5839920e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
added boot type based nand or emmc flash selection.
So machid based flash selection becomes obsolete.
Change-Id: I96fa43d31d23397fa249e02f62b905d6e4e67770
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
For 192MHz:
GCC_SDCC1_APPS_CFG_RCGR(0x1833008) set to 0x220b
GCC_SDCC1_APPS_M(0x183300c) set to 0x0
GCC_SDCC1_APPS_N(0X1833010) set to 0x0
GCC_SDCC1_APPS_D(0x1833014) set to 0x0
Change-Id: I2715b4428e4390f0b9b0b159e984a718d6c791a3
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
This patch adds support to enable flash using machid
Change-Id: I745a941d4219dc4cd29be96876710e15185ecb8f
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This changes includes update the Speed clock,
common clock update and dts nodes.
Change-Id: I673e8ccf191048fef966a8f6cd84858e1a3b824f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Only one SFP port can be enabled at time with
either SGMII or SGMII PLUS mode.
Mode shall be specified from dts for 1G or 2.5G
support respectively. Add below change to enable
SFP as this change is not mainlined.
gmac_cfg {
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
- phy_address = <0x1c>;
- napa_gpio = <39>;
/*
* 6 - SGMII_PLUS (2.5G),
* 8 - SGMII_FIBER (1G)
*/
+ switch_mac_mode = <8>;
+ sfp_tx_gpio = <27>;
+ sfp_rx_gpio = <29>;
};
};
Change-Id: I507be2b84b1f932802659abffa3288e304e0d411
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
This patch removes the support for dumpinfo_s structure to have
uniform EBICS0 bin for both sec and non-sec boots as the Read As Zero
(RAZ) flag has been enabled to protect code and data regions of TZ
The patchset applies to all the targets except IPQ5018 as the RAZ
flag enablement was not supported in IPQ5018
Change-Id: I63514284448de08926cd2c9b741f02859067044d
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
The CRASHDUMP RESET bit of TCSR_BOOT_MISC_DETECT Register
has to be set before reset from u-boot in the
crashdump collection path for TZ to differentiate between the
normal reset and crashdump reset from u-boot and
to retain the crash reason.
Change-Id: Ib623bfeab15d1bc230f4a8824218f1a3c4368fbb
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
Add support for ECO bit toggle during IPC start/stop
messages to allow BT subsystem to do self reset
Change-Id: I4d1d31a43ea8a002eb91cc42300677339c117d71
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
TCSR_BOOT_MISC_REG bits are not properly managed
for DLOAD implementation. Modify only necessary
bits to enable availability for new feature
implementations using TCSR_BOOT_MISC_REG.
Change-Id: I888a1bf6ce3654b0453c9ec2f87b4d5ff2a20de0
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
This changes remove pci phy deinit sequence and
also update the pci phy address
Change-Id: I9bae09958e395dfb509a17e472674f33fe214f1c
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change adds cmd_dpr as a common file,
so it will be reused in the future SoC.
dpr support added in Devsoc SoC.
Change-Id: I246a8f51c07c2f6952173bbd72e327ab1119af6e
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change will add the clock setting for qpic-serial nand
Change-Id: Iae53933423572e35126ceeb359b82d1078d09bf2
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch eliminates to maintain seperate dts file
for mmc flash. It enables flash node based
on machine id.
Change-Id: I67d95db162630a3bc84429e8a9338097e1e24619
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Updating this RDP to be based on AL02-C13 with all pcie enabled.
The extra feature is Alder 2G.
Change-Id: I817566ec6e3c95ce72c6b6ea379a73ef1f23ffe4
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
Currently if CONFIG_QCA8084_PHY is enabled means, it will build
all qca8084 functions required for both PHY & switch mode. But,
some ipq devices might uses anyone of them. So, add configs to
seperate the PHY & switch mode and define it in corresponding
defconfig file as per the need.
Also, some of the qca8084 functions will be used only for debug
purpose, those functions are moved under the config QCA8084_DEBUG.
Thereby, we can save some space in the u-boot.
Change-Id: I7e5f53869629a0c7cbbb12daf04ed782c9693623
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
