This patch enables support for USB 2.0 in AP-MI01.2
Change-Id: I4f848a403f3aae45a9f1cfa136781fbc7a37c35a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The pcie AUX clock source changed to XO as per
GCC frequency plan
Change-Id: If032831d3a9523ec214a62cbed2950ee5839920e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
mi01.2-qcn9160-c1 is derived from mi01.2.
This variant disables pci0 (enables usb3.0)
and supports qcn9160 on pcie2 port.
Change-Id: Ie0e2cd7f039fab9f80788f135c80285e61b00310
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
added boot type based nand or emmc flash selection.
So machid based flash selection becomes obsolete.
Change-Id: I96fa43d31d23397fa249e02f62b905d6e4e67770
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
For 192MHz:
GCC_SDCC1_APPS_CFG_RCGR(0x1833008) set to 0x220b
GCC_SDCC1_APPS_M(0x183300c) set to 0x0
GCC_SDCC1_APPS_N(0X1833010) set to 0x0
GCC_SDCC1_APPS_D(0x1833014) set to 0x0
Change-Id: I2715b4428e4390f0b9b0b159e984a718d6c791a3
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
This patch updates the CONFIG_SYS_PROMPT
from "ipq5332# " to "IPQ5332# "
Change-Id: I3c42fcc4aba23c092788c028761ddc9656cd32d9
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Updating the AL02-C7 configuration to support QCA8084 PHY
instead of QCA8075 PHY
Change-Id: Ie838d913caeb9dd933c6bd9fbdf8ee58563bdb7a
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
This patch adds support to enable flash using machid
Change-Id: I745a941d4219dc4cd29be96876710e15185ecb8f
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds support for new board variant AL02-C19.
This board variant consists of one internal radio,
Waikiki 5G in pci slot 0, Waikiki 6G in pci slot 2 and
SDX in pci slot 3.
Change-Id: I43e3b5890f6bd8f6d182e4c3acc540a89f9c4a34
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Bootconfig partition can have the MAGIC value 0xA3A3A1A1
if try_mode is enabled. Update the checks in smem APIs
Change-Id: I2fb71ff5812468f3f5ecd0153c35cab7d8e4bb44
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
This changes includes update the Speed clock,
common clock update and dts nodes.
Change-Id: I673e8ccf191048fef966a8f6cd84858e1a3b824f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
nSelectors is used in a loop from 0 to nSelectors to access selectorMtf
which is
UChar selectorMtf[BZ_MAX_SELECTORS];
so if nSelectors is bigger than BZ_MAX_SELECTORS it'll do an invalid memory
access
Fixes out of bounds access discovered while fuzzying karchive
This was reported as CVE-2019-12900
BZ2_decompress in decompress.c in bzip2 through 1.0.6 has an
out-of-bounds write when there are many selectors.
Change-Id: I536d2fe19d7182d4e51f76a502e8f0e72a2359ea
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Only one SFP port can be enabled at time with
either SGMII or SGMII PLUS mode.
Mode shall be specified from dts for 1G or 2.5G
support respectively. Add below change to enable
SFP as this change is not mainlined.
gmac_cfg {
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
- phy_address = <0x1c>;
- napa_gpio = <39>;
/*
* 6 - SGMII_PLUS (2.5G),
* 8 - SGMII_FIBER (1G)
*/
+ switch_mac_mode = <8>;
+ sfp_tx_gpio = <27>;
+ sfp_rx_gpio = <29>;
};
};
Change-Id: I507be2b84b1f932802659abffa3288e304e0d411
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
This patch removes the support for dumpinfo_s structure to have
uniform EBICS0 bin for both sec and non-sec boots as the Read As Zero
(RAZ) flag has been enabled to protect code and data regions of TZ
The patchset applies to all the targets except IPQ5018 as the RAZ
flag enablement was not supported in IPQ5018
Change-Id: I63514284448de08926cd2c9b741f02859067044d
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
"list_qcn9224_fuse" command will print the OEM ID, Secure boot enable
and OEM PK hash details of QCN9224 from all attached PCIe slots.
Change-Id: I87be2f58bcef6898a00f4e179c87f2dcb93a2604
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
The CRASHDUMP RESET bit of TCSR_BOOT_MISC_DETECT Register
has to be set before reset from u-boot in the
crashdump collection path for TZ to differentiate between the
normal reset and crashdump reset from u-boot and
to retain the crash reason.
Change-Id: Ib623bfeab15d1bc230f4a8824218f1a3c4368fbb
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
Add support for ECO bit toggle during IPC start/stop
messages to allow BT subsystem to do self reset
Change-Id: I4d1d31a43ea8a002eb91cc42300677339c117d71
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
Add build support for DB-MI01.1 and DB-MI02.1
Change-Id: I00a2698924813e52d196469630e271b0c3009aec
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
GPIO_PULL details updated on AP-MI01.1, AP-MI01.2, AP-MI01.4,
DB-MI01.1 and DB-MI02.1
SPI NOR added only in MI01.1 and removed from other RDP's
Renamed DB-MI01.2 to DB-MI01.1
Change-Id: Ic2c3467aa06d04dd5e759767a806b4905b0d118a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
