Add skip_pci_mask environment variable to skip pci enumeration
based on the bitmask. Also, removing the pci3 dts entry from
the RDP437 & RDP461 to skip pci3 enumeration.
Example - setenv skip_pci_mask 0xc
The above command will skip pci enumeration of bus 2 & 3.
Change-Id: Iff50acca07ffc026bed84a0d2372e6de0a3ba3a9
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Added JTAG ID, Serial number and Part type read.
Change-Id: Ia03724116230a157fc33406a97c641e3b5750d6a
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Added QCN92xx's SoC global reset and MHI reset in the fuse blow path.
So, the fuse blow can be retried after any failed attempts.
Added ANTI ROLLBACK fuse read.
Change-Id: Ibf255390ffc2086fcbfa9041dc0bcb612f8d9a4e
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
"list_qcn9224_fuse" command will print the OEM ID, Secure boot enable
and OEM PK hash details of QCN9224 from all attached PCIe slots.
Change-Id: I87be2f58bcef6898a00f4e179c87f2dcb93a2604
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
This change adds a new command to support the qcn9224 fusing.
Fuser blower binary should be transfered via tftp to Host and
using fuse_qcn9224 command, binary can be transfered to qcn9224.
qcn9224 will take care of the fusing.
sample command:
tftpboot fuse_blower.bin
fuse_qcn9224 0
Change-Id: Ie8cd73a2d49799100bd1f717cdc4b8dad070f9bd
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
This patch adds a new command support to detect the qcn9224 version.
Based on "detect_qcn9224" command, change configures the BAR0 on EP,
does the window mapping and reads the HW version register. Version
value will be populated in "qcn9224_version" env. Version env will
be zero if there is no qcn9224 attach.
Change-Id: I4f4477590b439f31b46cb0b895dc0d9f8279a064
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
The PCIE node is disabled by default in
the emulation platform
Change-Id: I51041186a57d08b58c1f7c85dd1a90fbeb24aac9
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes removes unwannted source for ipq806x
platform, therefore it saves more memory in flash
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia34c9843a5b32c2db57ec4b4977ab8c04875161b
This changes add SKU validation support in PCI driver
the valdiation api given as weak for non SKU supported platform.
Change-Id: I32985be1e06e9cb07d28edfba50299bb7eaa3cc5
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
This changes add pci 2 lane support in pci driver
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia4235c277e91d68366f6ae8aa16d8505a2ca5b05
This Fix will skip phy init sequence
for IPQ5018 because it doesn't need
any phy initialization.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: I781ea03eda933692d6a096c97d93d238b1e7063d
There is a change in reference clock(XO) frequency of
ipq6018(24MHz) from ipq807x(19.2MHz). Accordingly,
updated the phy init sequence of PCIe.
Change-Id: I86230187a46fec16a87acfaa17cfa27dc1eb728c
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Some cards are not working due to pcie reset.
So doing pcie reset with pcie reset gpio.
Change-Id: I0c631b116923b90bf94223d09e5662900a31244e
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Changed the assert and deassert sequence to enable the pcie
linkup for peripheral specific devices.
Change-Id: I2f93f818fe9f85ffa43fb5dff1a9cc67ae393183
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
1. Added pci entries in AP160 and AP160_2xx dts
2. The wifi pcie card requires to be powered on from GPIO
pins. This patch also adds the same in AP160 dts file and
enable it during PCIe configuration.
Change-Id: Icd8f5741d5df38d46640c78a7475853e77b873a9
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
As DK and AK does not have pci-phy entry making it as
applicable only for HK
Change-Id: I52d110f4012b867bb019859be9168b3aea68bfd4
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
If the PCIE cards are not connected, executing the pci
commands lead to the crash.
Change-Id: Id68ab1a39bfc3319d17af2fe6a3c8d4c1af039b0
Signed-off-by: smuthayy <smuthayy@codeaurora.org>
As the U-boot source is going to be common between ARM and MIPS
architecture , it is required to pick only the files specific
to the respective architectures during the build.
So, move the qca arm target specific common files to another
sub level by specifying the ARCH arm.
Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
When trying to access non-existent/unsupported PCI devices in
ls_pcie_read_config(), when ls_pcie_addr_valid() fails it returns
error code and fills in the result with 0xffffffff manually. But it
really should return zero to upper layer codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When trying to access non-existent/unsupported PCI devices in
imx_pcie_read_config(), when imx_pcie_addr_valid() fails it returns
error code and fills in the result with 0xffffffff manually. But it
really should return zero to upper layer codes.
Reported-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
This function looks up the controller and returns a pointer to each region
type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
A PCI bus may be a bridge device where the controller is the bridge's
parent. Add a function to return the controller device, given a PCI device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
