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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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ipq807x: Fix compiler warnings for PCI driver
Change-Id: I616ae06fe058b6bcfb1f9404625af002214650d1 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This commit is contained in:
Sham Muthayyan
Gerrit - the friendly Code Review server
parent
0195f6b90d
commit
168f7cdb7f
1 changed files with 53 additions and 50 deletions
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@ -99,23 +99,23 @@ DECLARE_GLOBAL_DATA_PTR;
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#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
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#define QSERDES_COM_VCO_TUNE_TIMER2 0x144
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#define QSERDES_COM_CMN_CONFIG 0x194
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#define QSERDES_COM_PLL_IVCO 0x48
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#define PCIE_QSERDES_COM_PLL_IVCO 0x48
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#define QSERDES_COM_HSCLK_SEL 0x178
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#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19C
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#define QSERDES_COM_CORE_CLK_EN 0x18C
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#define PCIE_QSERDES_COM_SVS_MODE_CLK_SEL 0x19C
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#define PCIE_QSERDES_COM_CORE_CLK_EN 0x18C
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#define QSERDES_COM_CORECLK_DIV 0x184
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#define QSERDES_COM_RESETSM_CNTRL 0xB4
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#define QSERDES_COM_BG_TIMER 0xC
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#define QSERDES_COM_SYSCLK_EN_SEL 0xAC
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#define QSERDES_COM_DEC_START_MODE0 0xD0
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#define QSERDES_COM_DIV_FRAC_START3_MODE0 0xE4
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#define QSERDES_COM_DIV_FRAC_START2_MODE0 0xE0
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#define QSERDES_COM_DIV_FRAC_START1_MODE0 0xDC
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#define PCIE_QSERDES_COM_BG_TIMER 0xC
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#define PCIE_QSERDES_COM_SYSCLK_EN_SEL 0xAC
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#define PCIE_QSERDES_COM_DEC_START_MODE0 0xD0
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#define PCIE_QSERDES_COM_DIV_FRAC_START3_MODE0 0xE4
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#define PCIE_QSERDES_COM_DIV_FRAC_START2_MODE0 0xE0
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#define PCIE_QSERDES_COM_DIV_FRAC_START1_MODE0 0xDC
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#define QSERDES_COM_LOCK_CMP3_MODE0 0x54
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#define QSERDES_COM_LOCK_CMP2_MODE0 0x50
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#define QSERDES_COM_LOCK_CMP1_MODE0 0x4C
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#define PCIE_QSERDES_COM_LOCK_CMP1_MODE0 0x4C
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#define QSERDES_COM_CLK_SELECT 0x174
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#define QSERDES_COM_SYS_CLK_CTRL 0x3C
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#define PCIE_QSERDES_COM_SYS_CLK_CTRL 0x3C
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#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x40
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#define QSERDES_COM_CP_CTRL_MODE0 0x78
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#define QSERDES_COM_PLL_RCTRL_MODE0 0x84
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@ -125,7 +125,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0xA8
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#define QSERDES_COM_VCO_TUNE_CTRL 0xC
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#define QSERDES_COM_SSC_EN_CENTER 0x10
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#define QSERDES_COM_SSC_PER1 0x1C
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#define PCIE_QSERDES_COM_SSC_PER1 0x1C
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#define QSERDES_COM_SSC_PER2 0x20
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#define QSERDES_COM_SSC_ADJ_PER1 0x14
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#define QSERDES_COM_SSC_ADJ_PER2 0x18
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@ -134,14 +134,14 @@ DECLARE_GLOBAL_DATA_PTR;
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#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x268
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#define QSERDES_TX_LANE_MODE 0x294
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#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x254
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#define QSERDES_TX_RCV_DETECT_LVL_2 0x2AC
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#define PCIE_QSERDES_TX_RCV_DETECT_LVL_2 0x2AC
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#define QSERDES_RX_SIGDET_ENABLES 0x510
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#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x51C
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x4D8
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4DC
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x4E0
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#define PCIE_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x51C
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#define PCIE_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x4D8
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#define PCIE_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4DC
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#define PCIE_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x4E0
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#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x448
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#define QSERDES_RX_UCDR_SO_GAIN 0x41C
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#define PCIE_QSERDES_RX_UCDR_SO_GAIN 0x41C
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#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x410
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#define QSERDES_COM_CLK_EP_DIV 0x74
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#define PCIE_USB3_PCS_ENDPOINT_REFCLK_DRIVE 0x854
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@ -347,6 +347,7 @@ DECLARE_GLOBAL_DATA_PTR;
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static unsigned int local_buses[] = { 0, 0 };
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struct pci_controller pci_hose[PCI_MAX_DEVICES];
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static int phy_initialised;
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extern int get_soc_version(uint32_t *soc_ver_major, uint32_t *soc_ver_minor);
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enum pcie_verion{
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PCIE_V0,
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@ -874,18 +875,20 @@ static int ipq_pcie_parse_dt(const void *fdt, int id,
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int ret;
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ret = get_soc_version(&soc_ver_major, &soc_ver_minor);
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if(soc_ver_major == 1) {
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err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pci_phy_gen2",
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&pcie->pci_phy);
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if (err < 0)
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goto err;
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pcie->is_gen3 = 0;
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} else if(soc_ver_major == 2) {
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err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pci_phy_gen3",
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&pcie->pci_phy);
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if (err < 0)
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goto err;
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pcie->is_gen3 = 1;
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if (!ret) {
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if(soc_ver_major == 1) {
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err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pci_phy_gen2",
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&pcie->pci_phy);
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if (err < 0)
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goto err;
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pcie->is_gen3 = 0;
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} else if(soc_ver_major == 2) {
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err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pci_phy_gen3",
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&pcie->pci_phy);
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if (err < 0)
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goto err;
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pcie->is_gen3 = 1;
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}
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} else {
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goto err;
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}
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@ -1002,23 +1005,23 @@ static const struct phy_regs pcie_phy_regs[] = {
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{ QSERDES_COM_VCO_TUNE_TIMER1, 0x000000ff },
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{ QSERDES_COM_VCO_TUNE_TIMER2, 0x0000001f },
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{ QSERDES_COM_CMN_CONFIG, 0x00000006 },
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{ QSERDES_COM_PLL_IVCO, 0x0000000f },
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{ PCIE_QSERDES_COM_PLL_IVCO, 0x0000000f },
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{ QSERDES_COM_HSCLK_SEL, 0x00000000 },
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{ QSERDES_COM_SVS_MODE_CLK_SEL, 0x00000001 },
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{ QSERDES_COM_CORE_CLK_EN, 0x00000020 },
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{ PCIE_QSERDES_COM_SVS_MODE_CLK_SEL, 0x00000001 },
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{ PCIE_QSERDES_COM_CORE_CLK_EN, 0x00000020 },
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{ QSERDES_COM_CORECLK_DIV, 0x0000000a },
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{ QSERDES_COM_RESETSM_CNTRL, 0x00000020 },
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{ QSERDES_COM_BG_TIMER, 0x00000009 },
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{ QSERDES_COM_SYSCLK_EN_SEL, 0x0000000a },
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{ QSERDES_COM_DEC_START_MODE0, 0x00000082 },
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{ QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00000003 },
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{ QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00000055 },
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{ QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00000055 },
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{ PCIE_QSERDES_COM_BG_TIMER, 0x00000009 },
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{ PCIE_QSERDES_COM_SYSCLK_EN_SEL, 0x0000000a },
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{ PCIE_QSERDES_COM_DEC_START_MODE0, 0x00000082 },
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{ PCIE_QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00000003 },
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{ PCIE_QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00000055 },
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{ PCIE_QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00000055 },
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{ QSERDES_COM_LOCK_CMP3_MODE0, 0x00000000 },
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{ QSERDES_COM_LOCK_CMP2_MODE0, 0x0000000D },
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{ QSERDES_COM_LOCK_CMP1_MODE0, 0x00000D04 },
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{ PCIE_QSERDES_COM_LOCK_CMP1_MODE0, 0x00000D04 },
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{ QSERDES_COM_CLK_SELECT, 0x00000033 },
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{ QSERDES_COM_SYS_CLK_CTRL, 0x00000002 },
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{ PCIE_QSERDES_COM_SYS_CLK_CTRL, 0x00000002 },
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{ QSERDES_COM_SYSCLK_BUF_ENABLE, 0x0000001f },
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{ QSERDES_COM_CP_CTRL_MODE0, 0x0000000b },
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{ QSERDES_COM_PLL_RCTRL_MODE0, 0x00000016 },
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@ -1028,7 +1031,7 @@ static const struct phy_regs pcie_phy_regs[] = {
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{ QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x00000001 },
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{ QSERDES_COM_VCO_TUNE_CTRL, 0x0000000a },
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{ QSERDES_COM_SSC_EN_CENTER, 0x00000001 },
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{ QSERDES_COM_SSC_PER1, 0x00000031 },
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{ PCIE_QSERDES_COM_SSC_PER1, 0x00000031 },
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{ QSERDES_COM_SSC_PER2, 0x00000001 },
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{ QSERDES_COM_SSC_ADJ_PER1, 0x00000002 },
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{ QSERDES_COM_SSC_ADJ_PER2, 0x00000000 },
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@ -1037,14 +1040,14 @@ static const struct phy_regs pcie_phy_regs[] = {
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{ QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x00000045 },
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{ QSERDES_TX_LANE_MODE, 0x00000006 },
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{ QSERDES_TX_RES_CODE_LANE_OFFSET, 0x00000002 },
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{ QSERDES_TX_RCV_DETECT_LVL_2, 0x00000012 },
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{ PCIE_QSERDES_TX_RCV_DETECT_LVL_2, 0x00000012 },
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{ QSERDES_RX_SIGDET_ENABLES, 0x0000001c },
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{ QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x00000014 },
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{ QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00000001 },
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{ QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00000000 },
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{ QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x000000db },
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{ PCIE_QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x00000014 },
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{ PCIE_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00000001 },
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{ PCIE_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00000000 },
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{ PCIE_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x000000db },
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{ QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x0000004b },
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{ QSERDES_RX_UCDR_SO_GAIN, 0x00000004 },
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{ PCIE_QSERDES_RX_UCDR_SO_GAIN, 0x00000004 },
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{ QSERDES_RX_UCDR_SO_GAIN_HALF, 0x00000004 },
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{ QSERDES_COM_CLK_EP_DIV, 0x00000019 },
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{ PCIE_USB3_PCS_ENDPOINT_REFCLK_DRIVE, 0x00000004 },
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@ -1210,7 +1213,7 @@ void pcie_phy_v2_init(struct ipq_pcie *pcie)
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qca_pcie_write_reg(pcie->pci_phy.start, PCIE_0_PCS_COM_SW_RESET, 0x0);
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qca_pcie_write_reg(pcie->pci_phy.start, PCIE_0_PCS_COM_START_CONTROL, 0x3);
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mdelay(5);
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return 0;
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return;
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}
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static int pci_ipq_ofdata_to_platdata(int id, struct ipq_pcie *pcie)
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{
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@ -1242,7 +1245,7 @@ static int pci_ipq_ofdata_to_platdata(int id, struct ipq_pcie *pcie)
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return 0;
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}
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__weak void ipq_wifi_pci_power_enable()
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__weak void ipq_wifi_pci_power_enable(void)
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{
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return;
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}
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