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ipq40xx: Changed the assert sequence for pcie linkup

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Changed the assert and deassert sequence to enable the pcie
linkup for peripheral specific devices.

Change-Id: I2f93f818fe9f85ffa43fb5dff1a9cc67ae393183
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This commit is contained in:
Rajkumar Ayyasamy 2018-03-07 15:02:02 +05:30 • committed by Gerrit - the friendly Code Review server
parent 318f41e4e4
commit 6173c50c84
1 changed files with 15 additions and 15 deletions
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30
drivers/pci/pci_ipq.c
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@ -644,6 +644,16 @@ void pci_controller_init_v1(struct ipq_pcie *pcie)
{
uint32_t val;
/* Assert cc_pcie20_mstr_axi_ares */
val = readl(pcie->pci_rst.start);
val |= PCIE_RST_CTRL_AXI_M_ARES;
writel(val, pcie->pci_rst.start);
/* Assert cc_pcie20_slv_axi_ares */
val = readl(pcie->pci_rst.start);
val |= PCIE_RST_CTRL_AXI_S_ARES;
writel(val, pcie->pci_rst.start);
/* Assert cc_pcie20_core_ares */
writel(PCIE_RST_CTRL_PIPE_ARES, pcie->pci_rst.start);
@ -657,31 +667,21 @@ void pci_controller_init_v1(struct ipq_pcie *pcie)
val |= PCIE_RST_CTRL_PIPE_PHY_AHB_ARES;
writel(val, pcie->pci_rst.start);
gpio_set_value(pcie->rst_gpio, GPIO_OUT_LOW);
/* Assert cc_pcie20_mstr_axi_ares */
val = readl(pcie->pci_rst.start);
val |= PCIE_RST_CTRL_AXI_M_ARES;
writel(val, pcie->pci_rst.start);
/* Assert cc_pcie20_mstr_sticky_ares */
val = readl(pcie->pci_rst.start);
val |= PCIE_RST_CTRL_AXI_M_STICKY_ARES;
writel(val, pcie->pci_rst.start);
/* Assert cc_pcie20_slv_axi_ares */
val = readl(pcie->pci_rst.start);
val |= PCIE_RST_CTRL_AXI_S_ARES;
writel(val, pcie->pci_rst.start);
gpio_set_value(pcie->rst_gpio, GPIO_OUT_LOW);
/* Assert cc_pcie20_ahb_ares; */
val = readl(pcie->pci_rst.start);
val |= PCIE_RST_CTRL_AHB_ARES;
writel(val, pcie->pci_rst.start);
/* DeAssert cc_pcie20_phy_ahb_ares */
/* DeAssert cc_pcie20_ahb_ares */
val = readl(pcie->pci_rst.start);
val &= ~(PCIE_RST_CTRL_AHB_ARES);
val &= ~(PCIE_RST_CTRL_PIPE_PHY_AHB_ARES);
writel(val, pcie->pci_rst.start);
/* DeAssert cc_pcie20_pciephy_phy_ares*/
@ -713,9 +713,9 @@ void pci_controller_init_v1(struct ipq_pcie *pcie)
val &= ~(PCIE_RST_CTRL_AXI_S_ARES);
writel(val, pcie->pci_rst.start);
/* DeAssert cc_pcie20_ahb_ares */
/* DeAssert cc_pcie20_phy_ahb_ares */
val = readl(pcie->pci_rst.start);
val &= ~(PCIE_RST_CTRL_PIPE_PHY_AHB_ARES);
val &= ~(PCIE_RST_CTRL_AHB_ARES);
writel(val, pcie->pci_rst.start);
}