This patch increases the CDR bandwidth to pass the
USB 3.0 Rx jitter tolerance test
Change-Id: Id58b71f4078ea5d60ab0b0d7bf93aa0a5d519e3c
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds a condition to power cycle the
SDX based on the current status of the e911 call.
Change-Id: Id3cf50cfb49a26151c98b7d52e18b9c487cfb935
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
This changes skips the re-initiation of ethernet
if boot fails, preventing ethernet from becoming unstable.
Change-Id: If46a54839db9986ed158b36bf9efb81c3412c88e
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This patch adds the XCFG configuration in HS PHY sequence
to reduce the noise in High Speed TX Eye
Change-Id: Iac430aa8bbd9ccc9a84c164578a1b6e35b3771f8
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The CRASHDUMP RESET bit of TCSR_BOOT_MISC_DETECT Register
has to be set in the crashdump collection path before reset
from u-boot for the TZ to differentiate between the
normal reset and crashdump reset from u-boot and
to retain the crash reason.
Change-Id: Ic74cec02bf749925e599ee12205257480a234064
Signed-off-by: Priyanka MA <quic_priyma@quicnic.com>
This patch adds support to power cycle the SDX device during
the IPQ crash scenario by toggling the full_power_on and reset
gpios.
Change-Id: Ifac2db5480c13456ef50b6d779691c5bf41f21b2
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
This change adds an additional condition to check for empty string as
env variable
Change-Id: Ica847b7af6d28094df54677fa7423e606699f5fe
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
With this change, Add option to support
prefixing crash dump files with timestamp prefix
Change-Id: I30343e6d7dc58376264dd34a4a3cd25bb34e65c6
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This change will read calibration data from the 0:ART partition and
apply it to the appropriate registers.
Change-Id: Ic9360c0fce229c1d1867ee897b811abc56d2b1c7
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
When xbl logs are disabled no logs came in uart console
due to gcc_blsp1_ahb_clk in disabled state.
This patch enables gcc_blsp1_ahb_clk in u-boot to avoid this issue.
Change-Id: I161b003096544e54d3d230027c2665e8fa3d0f5e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The main loop contains an eth init sequence,
to achieve this, remove the eth init sequence
from bootipq.avoid reinitialization.
Support for the IPQ5332 SoC has been added.
Change-Id: I18406dc90ba6845ce367215a55794ba5e400d5d3
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change creates Al02-c9 dts file to help with pci enumeration
Change-Id: I9a743de8ebbdc3f4ee43c14204ab1244e8945a12
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This patch removes the flash detection code in fdtfixup as it will be
taken care based on the boot flash type
Reference Commit:
425d52cd85 (avoid multiple machid for nand/mmc boot)
Change-Id: I51739ae539a568a1480a26fb9143be01306ce39a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch enables i2c usb and pci in AP-MI01.2 and AP-MI01.4.
Change-Id: I4f09485fcbad4247aa75676cb72dc4345405fdfc
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch enables support for USB 2.0 in AP-MI01.2
Change-Id: I4f848a403f3aae45a9f1cfa136781fbc7a37c35a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The pcie AUX clock source changed to XO as per
GCC frequency plan
Change-Id: If032831d3a9523ec214a62cbed2950ee5839920e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
added boot type based nand or emmc flash selection.
So machid based flash selection becomes obsolete.
Change-Id: I96fa43d31d23397fa249e02f62b905d6e4e67770
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
For 192MHz:
GCC_SDCC1_APPS_CFG_RCGR(0x1833008) set to 0x220b
GCC_SDCC1_APPS_M(0x183300c) set to 0x0
GCC_SDCC1_APPS_N(0X1833010) set to 0x0
GCC_SDCC1_APPS_D(0x1833014) set to 0x0
Change-Id: I2715b4428e4390f0b9b0b159e984a718d6c791a3
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
This patch adds support to enable flash using machid
Change-Id: I745a941d4219dc4cd29be96876710e15185ecb8f
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This changes includes update the Speed clock,
common clock update and dts nodes.
Change-Id: I673e8ccf191048fef966a8f6cd84858e1a3b824f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
