Changing the data type of phy_chip_id1 and phy_chip_id2 from
32-bit to 16-bit and initializing them to 0 to avoid any junk
value while shifting and concatenating them to form the final
phy_chip_id.
Change-Id: If96b01db9ec2b3c0a259ea3c98516d1f18a898ce
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
This change will add support for giga device
GD5F2GM7REYIG spi nand support.
Change-Id: I97772e0a8210bd5a6d41e10bbfbdd75b44e53108
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
update the port clock setting for qca8084 PHY with respect to
10M speed configuration.
Change-Id: I16403b155f31f37a6bdf828150ca2d0923a29f3e
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Previously 100M speed is not working in port 4 of MHT
by-pass mode. SGMII speed fixup required to dynamically
adjust the gcc clock based on the link-speed.
Still, this is requried only for port 4, because remaining
ports (1-3) will be taken care from switch core. So, added
speed fix for the by-mode support.
Change-Id: I495aad4b64de12ae7f57c0bdb9e0def08ad38681
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This patch adds the winbond W25N512GW and W25N02KWZEIR devices
and fixes the W25N01GWZEIG device id from 0xBA to 0xBA21,
W25N02JWZEIF device id from 0xBF to 0xBF22 and
W25N01JW device id from 0xBC to 0xBC21
Change-Id: Ic91800386446263477af06c6d39d9051a2dde3b9
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This changes updates the gcc common clk initialise
steps and adds support for obtaining bitmap
details from dts.
Change-Id: I55e895989823a4fbb97c638ad937ca48c00519c5
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change set SGMII mode and force mode based on
dts entries.
Change-Id: Ideaa1bb77fe8fb37a7e6b907a987f6dcac54917f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes enable both PHY and switch configure
simultaneously and also switch can be configure
to any port.
And also these changes enable dual MDIO bus support.
Change-Id: Ib86c8a15abb9a7a35aa86d87cef78ad917dd1a00
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Add skip_pci_mask environment variable to skip pci enumeration
based on the bitmask. Also, removing the pci3 dts entry from
the RDP437 & RDP461 to skip pci3 enumeration.
Example - setenv skip_pci_mask 0xc
The above command will skip pci enumeration of bus 2 & 3.
Change-Id: Iff50acca07ffc026bed84a0d2372e6de0a3ba3a9
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Added JTAG ID, Serial number and Part type read.
Change-Id: Ia03724116230a157fc33406a97c641e3b5750d6a
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
It has the capacity of 1Gbit, i.e., 128MB, so
the number of blocks has been updated to 1024.
1Gbits = 128MB = 2048(page) * 64 (pages per block) * 1024 (blocks)
Change-Id: I552776e4e151d16782db915c3ebae874c5c02696
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
Added new config called CONFIG_QCA8084_BYPASS_MODE and moved
all the qca8084 by-pass mode related code under it.
Change-Id: I4157960989cd67576803d494594869265fc81745
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Added QCA8084 by-pass mode support on MI01.1 RDP
Change-Id: I1a14729cac5463675f9cb0d15df3da76746aa81e
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
These changes update config as like below.
1.Config 100M, 1G as GMAC, 2.5G as XGMAC
2.Config MHT as XGMAC.
Change-Id: I0566f3a3d364931e8c8173c3604160f24c2439be
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Added QCN92xx's SoC global reset and MHI reset in the fuse blow path.
So, the fuse blow can be retried after any failed attempts.
Added ANTI ROLLBACK fuse read.
Change-Id: Ibf255390ffc2086fcbfa9041dc0bcb612f8d9a4e
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
This changes includes update the Speed clock,
common clock update and dts nodes.
Change-Id: I673e8ccf191048fef966a8f6cd84858e1a3b824f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
Only one SFP port can be enabled at time with
either SGMII or SGMII PLUS mode.
Mode shall be specified from dts for 1G or 2.5G
support respectively. Add below change to enable
SFP as this change is not mainlined.
gmac_cfg {
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
- phy_address = <0x1c>;
- napa_gpio = <39>;
/*
* 6 - SGMII_PLUS (2.5G),
* 8 - SGMII_FIBER (1G)
*/
+ switch_mac_mode = <8>;
+ sfp_tx_gpio = <27>;
+ sfp_rx_gpio = <29>;
};
};
Change-Id: I507be2b84b1f932802659abffa3288e304e0d411
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
