This patch updates the AP-MI04.1 PCIe configuration from
PCIe0 and PCIe1 to PCIe1 and PCIe2
Change-Id: If4aa155cc1005becd050fbc36d91d3764005c4c4
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Previously 100M speed is not working in port 4 of MHT
by-pass mode. SGMII speed fixup required to dynamically
adjust the gcc clock based on the link-speed.
Still, this is requried only for port 4, because remaining
ports (1-3) will be taken care from switch core. So, added
speed fix for the by-mode support.
Change-Id: I495aad4b64de12ae7f57c0bdb9e0def08ad38681
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This patch adds a condition to power cycle the
SDX based on the current status of the e911 call.
Change-Id: Id3cf50cfb49a26151c98b7d52e18b9c487cfb935
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
This patch removes the pcie2 and usb 3.0 support in AP-MI01.2-QCN9160
Change-Id: I1c2a6c9d27f1d2c75d3be505076626396d4c9d37
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This changes updates the gcc common clk initialise
steps and adds support for obtaining bitmap
details from dts.
Change-Id: I55e895989823a4fbb97c638ad937ca48c00519c5
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change set SGMII mode and force mode based on
dts entries.
Change-Id: Ideaa1bb77fe8fb37a7e6b907a987f6dcac54917f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes skips the re-initiation of ethernet
if boot fails, preventing ethernet from becoming unstable.
Change-Id: If46a54839db9986ed158b36bf9efb81c3412c88e
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes enable both PHY and switch configure
simultaneously and also switch can be configure
to any port.
And also these changes enable dual MDIO bus support.
Change-Id: Ib86c8a15abb9a7a35aa86d87cef78ad917dd1a00
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This patch adds the XCFG configuration in HS PHY sequence
to reduce the noise in High Speed TX Eye
Change-Id: Iac430aa8bbd9ccc9a84c164578a1b6e35b3771f8
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
AL02-C17 is based on AL02-C4. This variant
enables PCie0 and PCie2.
Change-Id: I67aa500bd13ec661a43b17c4cbcd56c9a6db8abc
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
Add rootfs section to authenticate signed rootfs image
Parse the hlos elf header and get the rootfs metadata offset
Reads metadata available at the end of hlos image and write to /tmp/metadata.bin
Calculate sha384 and write to /tmp/sha384_XXXXX file
Use /tmp/metadata.bin and /tmp/sha384_XXXXX to get rootfs auth by TZ
Change-Id: Iaa4bf6b0cfbae4f4a56187f80f2873cb69550051
Signed-off-by: Ram Chandra Jangir <quic_rjangir@quicinc.com>
The CRASHDUMP RESET bit of TCSR_BOOT_MISC_DETECT Register
has to be set in the crashdump collection path before reset
from u-boot for the TZ to differentiate between the
normal reset and crashdump reset from u-boot and
to retain the crash reason.
Change-Id: Ic74cec02bf749925e599ee12205257480a234064
Signed-off-by: Priyanka MA <quic_priyma@quicnic.com>
This patch adds support to power cycle the SDX device during
the IPQ crash scenario by toggling the full_power_on and reset
gpios.
Change-Id: Ifac2db5480c13456ef50b6d779691c5bf41f21b2
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
