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AU_LINUX_QSDK_FIG_TARGET_ALL.12.2.000.1820

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Merge AU_LINUX_QSDK_FIG_TARGET_ALL.12.2.000.1820 on remote branch

Change-Id: I5aa3de08ca9c7972c340322cc6e0f0edf4676dfe
Signed-off-by: Linux Build Service Account <lnxbuild@localhost>
This commit is contained in:
Linux Build Service Account 2023-03-10 08:37:26 -08:00
commit e9a0f2f77e
22 changed files with 1154 additions and 245 deletions
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4
arch/arm/dts/Makefile
View file

@ -92,14 +92,13 @@ dtb-$(CONFIG_ARCH_IPQ5018) += ipq5018-db-mp02.1.dtb \
endif
dtb-$(CONFIG_ARCH_IPQ5332) += ipq5332-emulation.dtb \
ipq5332-mi01.1.dtb \
ipq5332-mi01.2.dtb \
ipq5332-mi01.2-qcn9160-c1.dtb \
ipq5332-mi01.3.dtb \
ipq5332-mi01.4.dtb \
ipq5332-mi01.6.dtb \
ipq5332-mi01.7.dtb \
ipq5332-mi03.1.dtb \
ipq5332-mi04.1.dtb \
ipq5332-db-mi01.1.dtb \
ipq5332-db-mi02.1.dtb \
ipq5332-db-mi03.1.dtb
@ -121,6 +120,7 @@ dtb-$(CONFIG_ARCH_IPQ9574) += ipq9574-al01-c1.dtb \
ipq9574-al02-c9.dtb \
ipq9574-al02-c10.dtb \
ipq9574-al02-c13.dtb \
ipq9574-al02-c17.dtb \
ipq9574-al02-c18.dtb \
ipq9574-al02-c19.dtb \
ipq9574-db-al01-c1.dtb \

17
arch/arm/dts/ipq5332-mi01.3.dts
View file

@ -24,6 +24,7 @@
nand = "/nand-controller@79B0000";
mmc = "/sdhci@7804000";
usb0 = "/xhci@8a00000";
pci0 = "/pci@20000000";
pci1 = "/pci@18000000";
i2c0 = "/i2c@78B6000";
};
@ -180,10 +181,24 @@
};
};
pci0: pci@20000000 {
status = "ok";
perst_gpio = <38>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <38>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
pci1: pci@18000000 {
status = "ok";
perst_gpio = <47>;
lane = <2>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <47>;

235
arch/arm/dts/ipq5332-mi01.6.dts
View file

@ -14,26 +14,243 @@
*/
/dts-v1/;
#include "ipq5332-mi01.4.dts"
#include "ipq5332-soc.dtsi"
/ {
machid = <0x8060006>;
machid = <0x8060000>;
config_name = "config@mi01.6";
aliases {
console = "/serial@78AF000";
nand = "/nand-controller@79B0000";
mmc = "/sdhci@7804000";
usb0 = "/xhci@8a00000";
pci1 = "/pci@18000000";
i2c0 = "/i2c@78B6000";
};
serial@78AF000 {
status = "ok";
serial_gpio {
blsp0_uart_rx {
gpio = <18>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
blsp0_uart_tx {
gpio = <19>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
};
};
spi {
spi_gpio {
blsp0_spi_clk {
gpio = <14>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_mosi {
gpio = <15>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_miso {
gpio = <16>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_cs {
gpio = <17>;
func = <1>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
i2c@78B6000 {
i2c_gpio {
gpio1 {
gpio = <29>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_ENABLE>;
};
gpio2 {
gpio = <30>;
func = <3>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_ENABLE>;
};
};
};
nand: nand-controller@79B0000 {
nand_gpio {
qspi_dat3 {
gpio = <8>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat2 {
gpio = <9>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat1 {
gpio = <10>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_dat0 {
gpio = <11>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
qspi_cs_n {
gpio = <12>;
func = <2>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
qspi_clk {
gpio = <13>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
};
};
};
mmc: sdhci@7804000 {
mmc_gpio {
emmc_dat3 {
gpio = <8>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat2 {
gpio = <9>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat1 {
gpio = <10>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat0 {
gpio = <11>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_cmd{
gpio = <12>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_clk{
gpio = <13>;
func = <1>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_8MA>;
};
};
};
usb0: xhci@8a00000 {
ssphy = <1>;
};
pci1: pci@18000000 {
status = "ok";
perst_gpio = <47>;
lane = <2>;
pci_gpio {
pci_rst {
gpio = <47>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_10GBASE_R>;
qca808x_gpio = <16>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII0_RGMII4>;
qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>;
mdc_mdio_gpio = <27 28>;
qca8084_switch_enable = <1>;
/delete-property/napa_gpio;
qca8084_bypass_enable = <1>;
port_phyinfo {
port@0 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_id = <0>;
uniphy_mode = <PORT_WRAPPER_SGMII_PLUS>;
};
port@1 {
/delete-property/phy_address;
phy_type = <SFP_PHY_TYPE>;
phy_address = <4>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_id = <1>;
uniphy_mode = <PORT_WRAPPER_10GBASE_R>;
uniphy_mode = <PORT_WRAPPER_SGMII0_RGMII4>;
};
};
qca8084_swt_info {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_MAX>;
port@0 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
forced-speed = <2500>;
forced-duplex = <1>;
};
port@1 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@2 {
phy_address = <2>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@3 {
phy_address = <3>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@4 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
};
port@5 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
};
};
};

40
arch/arm/dts/ipq5332-mi01.7.dts
View file

@ -1,40 +0,0 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "ipq5332-mi01.1.dts"
/ {
machid = <0x8060007>;
config_name = "config@mi01.7";
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_10GBASE_R>;
qca808x_gpio = <16>;
qca808x_gpio_cnt = <1>;
mdc_mdio_gpio = <27 28>;
qca8084_switch_enable = <1>;
/delete-property/napa_gpio;
port_phyinfo {
port@1 {
/delete-property/phy_address;
phy_type = <SFP_PHY_TYPE>;
uniphy_id = <1>;
uniphy_mode = <PORT_WRAPPER_10GBASE_R>;
};
};
};
};

116
arch/arm/dts/ipq5332-mi01.1.dts → arch/arm/dts/ipq5332-mi04.1.dts
View file

@ -1,7 +1,7 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -16,16 +16,16 @@
/dts-v1/;
#include "ipq5332-soc.dtsi"
/ {
machid = <0x8060000>;
config_name = "config@mi01.1";
machid = <0x8060004>;
config_name = "config@mi04.1";
aliases {
console = "/serial@78AF000";
nand = "/nand-controller@79B0000";
mmc = "/sdhci@7804000";
usb0 = "/xhci@8a00000";
pci1 = "/pci@18000000";
i2c0 = "/i2c@78B6000";
pci0 = "/pci@20000000";
pci1 = "/pci@18000000";
};
serial@78AF000 {
@ -139,55 +139,24 @@
};
};
mmc: sdhci@7804000 {
mmc_gpio {
emmc_dat3 {
gpio = <8>;
func = <1>;
pci0: pci@20000000 {
status = "ok";
perst_gpio = <38>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <38>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat2 {
gpio = <9>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat1 {
gpio = <10>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_dat0 {
gpio = <11>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_cmd{
gpio = <12>;
func = <1>;
pull = <GPIO_PULL_UP>;
drvstr = <GPIO_8MA>;
};
emmc_clk{
gpio = <13>;
func = <1>;
pull = <GPIO_NO_PULL>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
usb0: xhci@8a00000 {
ssphy = <1>;
};
pci1: pci@18000000 {
status = "ok";
perst_gpio = <47>;
lane = <2>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <47>;
@ -197,61 +166,4 @@
};
};
};
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII0_RGMII4>;
qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>;
qca8084_switch_enable = <1>;
qca8084_bypass_enable = <1>;
port_phyinfo {
port@0 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_id = <0>;
uniphy_mode = <PORT_WRAPPER_SGMII_PLUS>;
};
port@1 {
phy_address = <4>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_id = <1>;
uniphy_mode = <PORT_WRAPPER_SGMII0_RGMII4>;
};
};
qca8084_swt_info {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_MAX>;
port@0 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
forced-speed = <2500>;
forced-duplex = <1>;
};
port@1 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@2 {
phy_address = <2>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@3 {
phy_address = <3>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@4 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
};
port@5 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
};
};
};
};

198
arch/arm/dts/ipq9574-al02-c17.dts Normal file
View file

@ -0,0 +1,198 @@
/*
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "ipq9574-soc.dtsi"
/ {
machid = <0x8051001>;
config_name = "config@al02-c17";
aliases {
console = "/serial@78B1000";
uart2 = "/serial@78B2000";
usb0 = "/xhci@8a00000";
pci0 = "/pci@28000000";
pci2 = "/pci@20000000";
nand = "/nand-controller@79B0000";
i2c0 = "/i2c@78B8000";
};
console: serial@78B1000 {
status = "ok";
serial_gpio {
blsp1_uart2_rx {
gpio = <34>;
func = <1>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_8MA>;
od_en = <GPIO_OD_DISABLE>;
};
blsp1_uart2_tx {
gpio = <35>;
func = <1>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_8MA>;
od_en = <GPIO_OD_DISABLE>;
};
};
};
spi {
spi_gpio {
blsp0_spi_clk {
gpio = <11>;
func = <1>;
pull = <GPIO_NO_PULL>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_mosi {
gpio = <14>;
func = <1>;
pull = <GPIO_NO_PULL>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_miso {
gpio = <13>;
func = <1>;
pull = <GPIO_NO_PULL>;
drvstr = <GPIO_8MA>;
};
blsp0_spi_cs {
gpio = <12>;
func = <1>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
nand: nand-controller@79B0000 {
status = "okay";
nand_gpio {
qspi_dat3 {
gpio = <0>;
func = <2>;
pull = <GPIO_NO_PULL>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
qspi_dat2 {
gpio = <1>;
func = <2>;
pull = <GPIO_NO_PULL>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
qspi_dat1 {
gpio = <2>;
func = <2>;
pull = <GPIO_NO_PULL>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
qspi_dat0 {
gpio = <3>;
func = <2>;
pull = <GPIO_NO_PULL>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
qspi_cs_n {
gpio = <4>;
func = <2>;
pull = <GPIO_NO_PULL>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
qspi_clk {
gpio = <5>;
func = <2>;
pull = <GPIO_NO_PULL>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
};
};
pci0: pci@28000000 {
status = "ok";
perst_gpio = <23>;
pci_gpio {
pci_rst {
gpio = <23>;
func = <0>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OD_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
};
};
pci2: pci@20000000 {
status = "ok";
perst_gpio = <29>;
pci_gpio {
pci_rst {
gpio = <29>;
func = <0>;
pull = <GPIO_PULL_DOWN>;
oe = <GPIO_OD_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
drvstr = <GPIO_8MA>;
};
};
};
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_PSGMII>;
switch_mac_mode1 = <PORT_WRAPPER_USXGMII>;
switch_mac_mode2 = <PORT_WRAPPER_USXGMII>;
qca807x_gpio = <60>;
qca807x_gpio_cnt = <1>;
aquantia_gpio = <36>;
aquantia_gpio_cnt = <1>;
aquantia_port = <4 5>;
aquantia_port_cnt = <2>;
mdc_mdio_gpio = <38 39>;
port_phyinfo {
port@0 {
phy_address = <16>;
phy_type = <QCA807x_PHY_TYPE>;
};
port@1 {
phy_address = <17>;
phy_type = <QCA807x_PHY_TYPE>;
};
port@2 {
phy_address = <18>;
phy_type = <QCA807x_PHY_TYPE>;
};
port@3 {
phy_address = <19>;
phy_type = <QCA807x_PHY_TYPE>;
};
port@4 {
phy_address = <8>;
phy_type = <AQ_PHY_TYPE>;
};
port@5 {
phy_address = <0>;
phy_type = <AQ_PHY_TYPE>;
};
};
};
};

28
board/qca/arm/ipq5332/ipq5332.c
View file

@ -318,7 +318,6 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_PCI_IPQ
void pcie_reset(int pcie_id)
{
#ifdef QCA_CLOCK_ENABLE
u32 reg_val;
switch(pcie_id) {
@ -359,10 +358,6 @@ void pcie_reset(int pcie_id)
break;
}
#else
return;
#endif
}
int ipq_validate_qfrom_fuse(unsigned int reg_add, int pos)
@ -464,6 +459,7 @@ void board_pci_deinit()
qca_gpio_deinit(gpio_node);
pcie_v2_clock_deinit(i);
pcie_reset(i);
}
return;
@ -731,6 +727,23 @@ static void usb_init_hsphy(void __iomem *phybase, int ssphy)
writel(XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM,
phybase + USB2PHY_USB_PHY_M31_XCFGI_11);
/* Adjust HSTX slew rate to 565 ps*/
/* Adjust PLL lock Time counter for release clock to 35uA */
/* Adjust Manual control ODT value to 38.02 Ohm */
writel(HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA |
ODT_VALUE_38_02_OHM, phybase + USB2PHY_USB_PHY_M31_XCFGI_4);
/*
* Enable to always turn on USB 2.0 TX driver
* when system is in USB 2.0 HS mode
*/
writel(USB2_0_TX_ENABLE, phybase + USB2PHY_USB_PHY_M31_XCFGI_1);
/* Adjust Manual control ODT value to 45.02 Ohm */
/* Adjust HSTX Pre-emphasis level to 0.55mA */
writel(ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
phybase + USB2PHY_USB_PHY_M31_XCFGI_5);
udelay(10);
writel(0, phybase + USB_PHY_UTMI_CTRL5);
@ -947,6 +960,11 @@ void set_flash_secondary_type(qca_smem_flash_info_t *smem)
return;
};
int get_soc_hw_version(void)
{
return readl(TCSR_SOC_HW_VERSION_REG);
}
#ifdef CONFIG_IPQ5332_EDMA
void set_function_select_as_mdc_mdio(void)
{

11
board/qca/arm/ipq5332/ipq5332.h
View file

@ -84,8 +84,18 @@ extern const add_node_t add_fdt_node[];
#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54
#define USB_PHY_REFCLK_CTRL 0xA0
#define USB_PHY_HS_PHY_CTRL2 0x64
#define USB2PHY_USB_PHY_M31_XCFGI_1 0xBC
#define USB2PHY_USB_PHY_M31_XCFGI_4 0xC8
#define USB2PHY_USB_PHY_M31_XCFGI_5 0xCC
#define USB2PHY_USB_PHY_M31_XCFGI_11 0xE4
#define USB2_0_TX_ENABLE BIT(2)
#define HSTX_SLEW_RATE_565PS 3
#define PLL_CHARGING_PUMP_CURRENT_35UA (3 << 3)
#define ODT_VALUE_38_02_OHM (3 << 6)
#define ODT_VALUE_45_02_OHM BIT(2)
#define HSTX_PRE_EMPHASIS_LEVEL_0_55MA (1)
#define UTMI_PHY_OVERRIDE_EN BIT(1)
#define SLEEPM BIT(1)
#define POR_EN BIT(1)
@ -103,6 +113,7 @@ extern const add_node_t add_fdt_node[];
#define APB_REG_UPHY_RX_RESCAL_CODE (16 << 8)
#define APB_REG_UPHY_RX_AFE_CAP1 (7 << 4)
#define APB_REG_UPHY_RX_AFE_RES1 (6 << 0)
#define TCSR_SOC_HW_VERSION_REG 0x194D000
/*
* OTP Register

3
drivers/net/Kconfig
View file

@ -153,3 +153,6 @@ config QCA8084_DEBUG
endif # QCA8084_PHY
config IPQ_QTI_BIT_BANGMII
bool "Enable MDIO Gpio bit bang support"
depends on BITBANGMII

1
drivers/net/Makefile
View file

@ -101,6 +101,7 @@ obj-$(CONFIG_IPQ5332_EDMA) += ipq5332/ipq5332_uniphy.o
endif
obj-$(CONFIG_IPQ_MDIO) += ipq_common/ipq_mdio.o
obj-$(CONFIG_IPQ_QTI_BIT_BANGMII) += ipq_common/ipq_bitbangmii.o
obj-$(CONFIG_GEPHY) += ipq_common/ipq_gephy.o
obj-$(CONFIG_QCA8075_PHY) += ipq_common/ipq_qca8075.o
obj-$(CONFIG_QCA8084_PHY) += ipq_common/ipq_qca8084.o

35
drivers/net/ipq5332/ipq5332_edma.c
View file

@ -76,6 +76,7 @@ extern void ipq_qca8084_switch_hw_reset(int gpio);
extern void ipq5332_xgmac_sgmiiplus_speed_set(int port, int speed, int status);
extern void ppe_uniphy_refclk_set_25M(uint32_t uniphy_index);
extern void qca8033_phy_reset(void);
extern void ipq5332_gmac_port_disable(int port);
#ifdef CONFIG_ATHRS17C_SWITCH
extern void ppe_uniphy_set_forceMode(uint32_t uniphy_index);
extern int ipq_qca8337_switch_init(ipq_s17c_swt_cfg_t *s17c_swt_cfg);
@ -909,6 +910,7 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
static fal_port_speed_t old_speed[IPQ5332_PHY_MAX] =
{[0 ... IPQ5332_PHY_MAX-1] = FAL_SPEED_BUTT};
static fal_port_speed_t curr_speed[IPQ5332_PHY_MAX];
static int current_active_port = -1, previous_active_port = -1;
fal_port_duplex_t duplex;
char *lstatus[] = {"up", "Down"};
char *dp[] = {"Half", "Full"};
@ -917,12 +919,45 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
int phy_addr = -1, ret = -1;
phy_info_t *phy_info;
int sgmii_mode = EPORT_WRAPPER_SGMII0_RGMII4, sfp_mode = -1;
char *active_port = NULL;
active_port = getenv("active_port");
if (active_port != NULL) {
current_active_port = simple_strtol(active_port, NULL, 10);
if (current_active_port < 0 || current_active_port > 1)
printf("active_port must be either 0 or 1\n");
} else {
current_active_port = -1;
}
if (previous_active_port != current_active_port && current_active_port != -1) {
previous_active_port = current_active_port;
printf("Port%d has been set as the active_port\n", current_active_port);
}
/*
* Check PHY link, speed, Duplex on all phys.
* we will proceed even if single link is up
* else we will return with -1;
*/
for (i = 0; i < IPQ5332_PHY_MAX; i++) {
if (current_active_port != -1 && i != current_active_port) {
ipq5332_gmac_port_disable(i);
ppe_port_bridge_txmac_set(i + 1, 1);
old_speed[i] = FAL_SPEED_BUTT;
/*
* Old speed has been set as FAL_SPEED_BUTT here so that
* if again the previous active_port is made as active,
* the configurations required will be done again and MAC
* would be enabled.
*
* Note that only for the active port TX/RX MAC would be
* enabled and for all other ports, the same would be
* disabled.
*/
continue;
}
phy_info = port_info[i]->phy_info;
if (phy_info->phy_type == UNUSED_PHY_TYPE)
continue;

2
drivers/net/ipq5332/ipq5332_ppe.c
View file

@ -180,7 +180,7 @@ static void ipq5332_vsi_setup(int vsi, uint8_t group_mask)
/*
* ipq5332_gmac_port_disable()
*/
static void ipq5332_gmac_port_disable(int port)
void ipq5332_gmac_port_disable(int port)
{
ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_ENABLE + (0x200 * port), 0x70);
ipq5332_ppe_reg_write(IPQ5332_PPE_MAC_SPEED + (0x200 * port), 0x2);

154
drivers/net/ipq_common/ipq_bitbangmii.c Normal file
View file

@ -0,0 +1,154 @@
/*
* Copyright (c) 2012 - 2013,2016-2017, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <miiphy.h>
#include <linux/compat.h>
#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
struct bitbang_nodes {
int mdio;
int mdc;
} __attribute__ ((aligned(8)));
#define MAX_MDIO_BUS 2
struct bitbang_nodes ipq_mdio_gpio[MAX_MDIO_BUS];
static int ipq_mii_init(struct bb_miiphy_bus *bus)
{
struct bitbang_nodes *bb_node = bus->priv;
struct bitbang_nodes *bb_node_base = &ipq_mdio_gpio[0];
int gpio_node, i = 0;
if (bb_node_base == bb_node) {
gpio_node = fdt_path_offset(gd->fdt_blob,
"/ess-switch/mdiobitbang0");
if (gpio_node >= 0)
qca_gpio_init(gpio_node);
} else {
gpio_node = fdt_path_offset(gd->fdt_blob,
"/ess-switch/mdiobitbang1");
if (gpio_node >= 0)
qca_gpio_init(gpio_node);
}
for (gpio_node = fdt_first_subnode(gd->fdt_blob, gpio_node);
gpio_node > 0;
gpio_node = fdt_next_subnode(gd->fdt_blob, gpio_node), ++i) {
if (i)
bb_node->mdio = fdtdec_get_uint(gd->fdt_blob,
gpio_node, "gpio", 0);
else
bb_node->mdc = fdtdec_get_uint(gd->fdt_blob,
gpio_node, "gpio", 0);
}
return 0;
}
static int ipq_mii_mdio_active(struct bb_miiphy_bus *bus)
{
struct bitbang_nodes *bb_node = bus->priv;
unsigned int *gpio_base;
gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(bb_node->mdio);
writel((readl(gpio_base) | (1 << GPIO_IN_OUT_BIT)), gpio_base);
gpio_set_value(bb_node->mdio, 1);
return 0;
}
static int ipq_mii_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct bitbang_nodes *bb_node = bus->priv;
unsigned int *gpio_base;
gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(bb_node->mdio);
writel((readl(gpio_base) & ~(1 << GPIO_IN_OUT_BIT)), gpio_base);
gpio_set_value(bb_node->mdio, 0);
return 0;
}
static int ipq_mii_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct bitbang_nodes *bb_node = bus->priv;
gpio_set_value(bb_node->mdio, v);
return 0;
}
static int ipq_mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct bitbang_nodes *bb_node = bus->priv;
*v = gpio_get_value(bb_node->mdio);
return 0;
}
static int ipq_mii_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct bitbang_nodes *bb_node = bus->priv;
gpio_set_value(bb_node->mdc, v);
return 0;
}
static int ipq_mii_delay(struct bb_miiphy_bus *bus)
{
ndelay(350);
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = "MDIO0",
.init = ipq_mii_init,
.mdio_active = ipq_mii_mdio_active,
.mdio_tristate = ipq_mii_mdio_tristate,
.set_mdio = ipq_mii_set_mdio,
.get_mdio = ipq_mii_get_mdio,
.set_mdc = ipq_mii_set_mdc,
.delay = ipq_mii_delay,
.priv = &ipq_mdio_gpio[0],
},
{
.name = "MDIO1",
.init = ipq_mii_init,
.mdio_active = ipq_mii_mdio_active,
.mdio_tristate = ipq_mii_mdio_tristate,
.set_mdio = ipq_mii_set_mdio,
.get_mdio = ipq_mii_get_mdio,
.set_mdc = ipq_mii_set_mdc,
.delay = ipq_mii_delay,
.priv = &ipq_mdio_gpio[1],
},
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);

177
drivers/net/ipq_common/ipq_mdio.c
View file

@ -27,11 +27,23 @@
#define pr_debug(fmt, args...)
#endif
#define MDIO_DEFAULT 0
#define MDIO_BITBANG 1
static int mdio_mode = 0;
static int bus_no = 0;
struct ipq_mdio_data {
struct mii_bus *bus;
int phy_irq[PHY_MAX_ADDR];
};
void ipq_set_mdio_mode(const int mode, const int bus)
{
mdio_mode = mode;
bus_no = bus;
}
static int ipq_mdio_wait_busy(void)
{
int i;
@ -156,109 +168,136 @@ int ipq_mdio_read1(int mii_id, int regnum, ushort *data)
return val;
}
int ipq_mdio_write(int mii_id, int regnum, u16 value)
{
u32 cmd;
#ifdef CONFIG_BITBANGMII
char name[16];
if (regnum & MII_ADDR_C45) {
unsigned int mmd = (regnum >> 16) & 0x1F;
unsigned int reg = regnum & 0xFFFF;
if (mdio_mode == MDIO_BITBANG) {
snprintf(name, sizeof(name), "MDIO%d", bus_no);
writel(CTRL_0_REG_C45_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
bb_miiphy_write_v2(name, mii_id, regnum, value);
} else
#endif
{
if (regnum & MII_ADDR_C45) {
unsigned int mmd = (regnum >> 16) & 0x1F;
unsigned int reg = regnum & 0xFFFF;
/* Issue the phy address and reg */
writel((mii_id << 8) | mmd,
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
writel(CTRL_0_REG_C45_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
/* Issue the phy address and reg */
writel((mii_id << 8) | mmd,
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
/* issue read command */
cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
/* issue read command */
cmd = MDIO_CTRL_4_ACCESS_START |
MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
if (ipq_mdio_wait_busy())
return -ETIMEDOUT;
} else {
writel(CTRL_0_REG_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
/* Issue the phy addreass and reg */
writel((mii_id << 8 | regnum),
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
}
/* Issue a write data */
writel(value, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
if (regnum & MII_ADDR_C45) {
cmd = MDIO_CTRL_4_ACCESS_START |
MDIO_CTRL_4_ACCESS_CODE_C45_WRITE ;
} else {
cmd = MDIO_CTRL_4_ACCESS_START |
MDIO_CTRL_4_ACCESS_CODE_WRITE ;
}
writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
/* Wait for write complete */
if (ipq_mdio_wait_busy())
return -ETIMEDOUT;
} else {
writel(CTRL_0_REG_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
/* Issue the phy addreass and reg */
writel((mii_id << 8 | regnum),
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
}
/* Issue a write data */
writel(value, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
if (regnum & MII_ADDR_C45) {
cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_WRITE ;
} else {
cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_WRITE ;
}
writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
/* Wait for write complete */
if (ipq_mdio_wait_busy())
return -ETIMEDOUT;
return 0;
}
int ipq_mdio_read(int mii_id, int regnum, ushort *data)
{
u32 val,cmd;
#ifdef CONFIG_BITBANGMII
char name[16];
if (mdio_mode == MDIO_BITBANG) {
if (regnum & MII_ADDR_C45) {
snprintf(name, sizeof(name), "MDIO%d", bus_no);
unsigned int mmd = (regnum >> 16) & 0x1F;
unsigned int reg = regnum & 0xFFFF;
bb_miiphy_read_v2(name, mii_id, regnum,
(unsigned short *)&val);
} else
#endif
{
if (regnum & MII_ADDR_C45) {
writel(CTRL_0_REG_C45_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
unsigned int mmd = (regnum >> 16) & 0x1F;
unsigned int reg = regnum & 0xFFFF;
/* Issue the phy address and reg */
writel((mii_id << 8) | mmd,
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
writel(CTRL_0_REG_C45_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
/* Issue the phy address and reg */
writel((mii_id << 8) | mmd,
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
/* issue read command */
cmd = MDIO_CTRL_4_ACCESS_START |
MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
} else {
writel(CTRL_0_REG_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
/* Issue the phy address and reg */
writel((mii_id << 8 | regnum ) ,
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
/* issue read command */
cmd = MDIO_CTRL_4_ACCESS_START |
MDIO_CTRL_4_ACCESS_CODE_READ ;
}
/* issue read command */
cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
} else {
writel(CTRL_0_REG_DEFAULT_VALUE,
IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
/* Issue the phy address and reg */
writel((mii_id << 8 | regnum ) ,
IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
/* issue read command */
cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_READ ;
}
/* issue read command */
writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
if (ipq_mdio_wait_busy())
return -ETIMEDOUT;
if (regnum & MII_ADDR_C45) {
cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_READ;
writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
if (ipq_mdio_wait_busy())
return -ETIMEDOUT;
if (regnum & MII_ADDR_C45) {
cmd = MDIO_CTRL_4_ACCESS_START |
MDIO_CTRL_4_ACCESS_CODE_C45_READ;
writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
if (ipq_mdio_wait_busy())
return -ETIMEDOUT;
}
/* Read data */
val = readl(IPQ_MDIO_BASE + MDIO_CTRL_3_REG);
}
/* Read data */
val = readl(IPQ_MDIO_BASE + MDIO_CTRL_3_REG);
if (data != NULL)
*data = val;

5
drivers/net/ipq_common/ipq_phy.h
View file

@ -159,6 +159,11 @@ typedef struct {
u32 forced_duplex;
}phy_info_t;
typedef struct {
u32 mode;
u32 bus_no;
}mdio_info_t;
struct phy_ops {
u8 (*phy_get_link_status) (u32 dev_id, u32 phy_id);
u32 (*phy_get_duplex) (u32 dev_id, u32 phy_id,

230
drivers/net/phy/miiphybb.c
View file

@ -5,6 +5,8 @@
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -20,6 +22,17 @@
#define BB_MII_RELOCATE(v,off) (v += (v?off:0))
#define MDIO_READ 2
#define MDIO_WRITE 1
#define MDIO_C45 (1<<15)
#define MDIO_C45_ADDR (MDIO_C45 | 0)
#define MDIO_C45_READ (MDIO_C45 | 3)
#define MDIO_C45_WRITE (MDIO_C45 | 1)
#define MDIO_SETUP_TIME 10
#define MDIO_HOLD_TIME 10
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_BITBANGMII_MULTI
@ -150,8 +163,8 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
* Utility to send the preamble, address, and register (common to read
* and write).
*/
static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
unsigned char addr, unsigned char reg)
static void miiphy_pre(struct bb_miiphy_bus *bus, int read,
unsigned int addr, unsigned int reg)
{
int j;
@ -172,24 +185,35 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
bus->delay(bus);
}
/* send the start bit (01) and the read opcode (10) or write (10) */
/* send the start bit (01) and the read opcode (10) or write (10)
* Clause 45 operation uses 00 for the start and 11, 10 for read/write
*/
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 1);
if (read & MDIO_C45)
bus->set_mdio(bus, 0);
else
bus->set_mdio(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, read);
if (read & MDIO_C45)
bus->set_mdio(bus, ((read >> 1) & 1));
else
bus->set_mdio(bus, read);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, !read);
if (read & MDIO_C45)
bus->set_mdio(bus, ((read >> 0) & 1));
else
bus->set_mdio(bus, !read);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
@ -223,6 +247,135 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
}
}
static int bb_miiphy_cmd_addr(struct bb_miiphy_bus *bus, unsigned phy_addr,
unsigned int reg_addr)
{
unsigned int dev_reg = (reg_addr >> 16) & 0x1F;
unsigned int reg = reg_addr & 0xFFFF;
int v, i;
miiphy_pre (bus, MDIO_C45_ADDR, phy_addr, dev_reg);
/* send the turnaround (10) */
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
for (i = 15; i >= 0; i--) {
bus->set_mdc(bus, 0);
bus->set_mdio(bus, ((reg >> i) & 1));
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
}
/* tri-state our MDIO I/O pin so we can read */
bus->set_mdc(bus, 0);
bus->mdio_tristate(bus);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->get_mdio(bus, &v);
bus->set_mdc(bus, 0);
return dev_reg;
}
/*****************************************************************************
*
* Read a MII PHY register V2.
* This API support C45 support
* Returns:
* 0 on success
*/
int bb_miiphy_read_v2(const char *devname, unsigned phy_addr,
unsigned int reg, unsigned short *value)
{
short rdreg; /* register working value */
int v;
int j; /* counter */
struct bb_miiphy_bus *bus;
int phy_reg;
bus = bb_miiphy_getbus(devname);
if (bus == NULL) {
return -1;
}
if (value == NULL) {
puts("NULL value pointer\n");
return -1;
}
if (reg & MII_ADDR_C45) {
phy_reg = bb_miiphy_cmd_addr(bus, phy_addr, reg);
miiphy_pre(bus, MDIO_C45_READ, phy_addr, phy_reg);
} else {
miiphy_pre(bus, 1, phy_addr, reg);
}
/* tri-state our MDIO I/O pin so we can read */
bus->set_mdc(bus, 0);
bus->mdio_tristate(bus);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
/* check the turnaround bit: the PHY should be driving it to zero */
bus->get_mdio(bus, &v);
if (v != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
bus->set_mdc(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
}
/* There is no PHY, set value to 0xFFFF and return */
*value = 0xFFFF;
return -1;
}
bus->set_mdc(bus, 0);
bus->delay(bus);
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
bus->set_mdc(bus, 1);
bus->delay(bus);
rdreg <<= 1;
bus->get_mdio(bus, &v);
rdreg |= (v & 0x1);
bus->set_mdc(bus, 0);
bus->delay(bus);
}
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
*value = rdreg;
#ifdef DEBUG
printf ("miiphy_read_v2(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
#endif
return 0;
}
/*****************************************************************************
*
* Read a MII PHY register.
@ -304,6 +457,71 @@ int bb_miiphy_read(const char *devname, unsigned char addr,
}
/*****************************************************************************
*
* Write a MII PHY register V2.
* This API support C45 support
* Returns:
* 0 on success
*/
int bb_miiphy_write_v2(const char *devname, unsigned int phy_addr,
unsigned int reg, unsigned short value)
{
struct bb_miiphy_bus *bus;
int j; /* counter */
unsigned int phy_reg;
bus = bb_miiphy_getbus(devname);
if (bus == NULL) {
/* Bus not found! */
return -1;
}
if (reg & MII_ADDR_C45) {
phy_reg = bb_miiphy_cmd_addr(bus, phy_addr, reg);
miiphy_pre(bus, MDIO_C45_WRITE, phy_addr, phy_reg);
} else {
miiphy_pre(bus, 0, phy_addr, reg);
}
/* send the turnaround (10) */
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
bus->set_mdc(bus, 0);
if ((value & 0x00008000) == 0) {
bus->set_mdio(bus, 0);
} else {
bus->set_mdio(bus, 1);
}
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
value <<= 1;
}
/*
* Tri-state the MDIO line.
*/
bus->mdio_tristate(bus);
bus->set_mdc(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
return 0;
}
/*****************************************************************************
*
* Write a MII PHY register.

4
drivers/pci/pci_ipq.c
View file

@ -670,7 +670,7 @@ static const struct phy_regs pcie_phy_v2_x2_init_seq_ipq[] = {
};
static const struct phy_regs pcie_phy_v2_init_seq_ipq[] = {
#if !defined(CONFIG_IPQ6018)
#if defined(CONFIG_IPQ807x)
{ PCS_COM_POWER_DOWN_CONTROL, 0x00000001},
{ PCIE_0_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x00000018},
{ PCIE_0_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x00000001},
@ -928,7 +928,7 @@ static const struct phy_regs pcie_phy_v2_init_seq_ipq[] = {
{ PCIE_0_PCS_COM_SW_RESET, 0x00000000},
{ PCIE_0_PCS_COM_START_CONTROL, 0x00000002},
{ PCIE_0_PCS_COM_START_CONTROL, 0x00000003},
#else
#elif defined(CONFIG_IPQ6018)
{ PCIE_0_PCS_COM_POWER_DOWN_CONTROL, 0x03 },
{ PCIE_0_QSERDES_PLL_SSC_PER1, 0x7D },
{ PCIE_0_QSERDES_PLL_SSC_PER2, 0x01 },

4
include/dt-bindings/qcom/eth-ipq9574.h
View file

@ -49,3 +49,7 @@
#define QCA8084_PHY_TYPE 0x6
#define UNUSED_PHY_TYPE 0xFF
#endif
/* MDIO config */
#define MDIO_MODE_DEFAULT 0
#define MDIO_MODE_BITBANG 1

5
include/miiphy.h
View file

@ -90,6 +90,11 @@ int bb_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int bb_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
int bb_miiphy_read_v2(const char *devname, unsigned int addr,
unsigned int reg, unsigned short *value);
int bb_miiphy_write_v2(const char *devname, unsigned int addr,
unsigned int reg, unsigned short value);
#endif
/* phy seed setup */

4
tools/pack.py
View file

@ -2262,7 +2262,7 @@ class Pack(object):
flinfo.chipsize, blocksize, chipsize, root_part)
self.partitions = mibib_qcn9224.get_parts()
script.append('if test "$machid" = "8050301" || test "$machid" = "8050501" || test "$machid" = "8050601" || test "$machid" = "8050701" || test "$machid" = "8050801" || test "$machid" = "8050901" || test "$machid" = "8050a01" || test "$machid" = "8050b01" || test "$machid" = "8050c01" || test "$machid" = "8050d01" || test "$machid" = "8050e01" || test "$machid" = "8050f01" || test "$machid" = "0x8051101" || test "$machid" = "8051201" || test "$machid" = "8050002" || test "$machid" = "8050102"; then\n', fatal=False)
script.append('if test "$machid" = "8050301" || test "$machid" = "8050501" || test "$machid" = "8050601" || test "$machid" = "8050701" || test "$machid" = "8050801" || test "$machid" = "8050901" || test "$machid" = "8050a01" || test "$machid" = "8050b01" || test "$machid" = "8050c01" || test "$machid" = "8050d01" || test "$machid" = "8050e01" || test "$machid" = "8050f01" || test "$machid" = "8051001" || test "$machid" = "0x8051101" || test "$machid" = "8051201" || test "$machid" = "8050002" || test "$machid" = "8050102"; then\n', fatal=False)
ret = self.__gen_flash_script(script, flinfo, root, True)
if ret == 0:
return 0 #Issue in packing al+wkk single-image
@ -2288,7 +2288,7 @@ class Pack(object):
gpt = GPT(part_fname_qcn9224, flinfo.pagesize, flinfo.blocksize, flinfo.chipsize)
self.partitions = gpt.get_parts()
script.append('if test "$machid" = "8050301" || test "$machid" = "8050501" || test "$machid" = "8050601" || test "$machid" = "8050701" || test "$machid" = "8050801" || test "$machid" = "8050901" || test "$machid" = "8050a01" || test "$machid" = "8050b01" || test "$machid" = "8050c01" || test "$machid" = "8050d01" || test "$machid" = "8050e01" || test "$machid" = "8050f01" || test "$machid" = "0x8051101" || test "$machid" = "8051201" || test "$machid" = "8050002" || test "$machid" = "8050102"; then\n', fatal=False)
script.append('if test "$machid" = "8050301" || test "$machid" = "8050501" || test "$machid" = "8050601" || test "$machid" = "8050701" || test "$machid" = "8050801" || test "$machid" = "8050901" || test "$machid" = "8050a01" || test "$machid" = "8050b01" || test "$machid" = "8050c01" || test "$machid" = "8050d01" || test "$machid" = "8050e01" || test "$machid" = "8050f01" || test "$machid" = "8051001" || test "$machid" = "0x8051101" || test "$machid" = "8051201" || test "$machid" = "8050002" || test "$machid" = "8050102"; then\n', fatal=False)
ret = self.__gen_flash_script(script, flinfo, root, True)
if ret == 0:
return 0 #Issue in packing al+wkk single-image

123
tools/sysupgrade.c
View file

@ -45,6 +45,7 @@
#define SBL_HDR_RESERVED 12
#define UBI_EC_HDR_MAGIC 0x55424923
#define UBI_VID_HDR_MAGIC 0x55424921
#define NO_OF_PROGRAM_HDRS 3
struct image_section sections[] = {
{
@ -60,6 +61,19 @@ struct image_section sections[] = {
.section_type = HLOS_TYPE,
.type = "hlos",
.max_version = MAX_HLOS_VERSION,
.tmp_file = TMP_FILE_DIR,
.pre_op = parse_elf_image_phdr,
.file = TMP_FILE_DIR,
.version_file = HLOS_VERSION_FILE,
.is_present = NOT_PRESENT,
.img_code = "0x17"
},
{
.section_type = HLOS_TYPE,
.type = "rootfs",
.max_version = MAX_HLOS_VERSION,
.tmp_file = TMP_FILE_DIR,
.pre_op = compute_sha384,
.file = TMP_FILE_DIR,
.version_file = HLOS_VERSION_FILE,
.is_present = NOT_PRESENT,
@ -215,6 +229,7 @@ int get_sections(void)
if (data_size == -1 && !strncmp(sec->type, "ubi", strlen("ubi")))
continue;
if (!strncmp(file->d_name, sec->type, strlen(sec->type))) {
strlcat(sec->file, file->d_name, sizeof(sec->file));
if (sec->pre_op) {
strlcat(sec->tmp_file, file->d_name,
sizeof(sec->tmp_file));
@ -222,9 +237,6 @@ int get_sections(void)
printf("Error extracting kernel from ubi\n");
return 0;
}
} else {
strlcat(sec->file, file->d_name,
sizeof(sec->file));
}
if (!check_mbn_elf(&sec)) {
closedir(dir);
@ -264,6 +276,8 @@ int load_sections(void)
if (data_size == -1 && !strncmp(sec->type, "ubi", strlen("ubi")))
continue;
if (!strncmp(file->d_name, sec->type, strlen(sec->type))) {
strlcat(sec->file, file->d_name, sizeof(sec->file));
if (sec->pre_op) {
strlcat(sec->tmp_file, file->d_name,
sizeof(sec->tmp_file));
@ -273,9 +287,6 @@ int load_sections(void)
closedir(dir);
return 0;
}
} else {
strlcat(sec->file, file->d_name,
sizeof(sec->file));
}
sec->is_present = PRESENT;
break;
@ -869,6 +880,27 @@ int extract_kernel_binary(struct image_section *section)
return 1;
}
/**
* The digest functions output the message digest of a supplied file and
* write sha384 to /tmp/sha384_keyXXXXXX file
*/
int compute_sha384(struct image_section *section)
{
char sha384_hash[] = "/tmp/sha384_keyXXXXXX";
char command[300];
int retval;
snprintf(command, sizeof(command),
"openssl dgst -sha384 -binary -out %s %s", sha384_hash, section->tmp_file);
retval = system(command);
if (retval != 0) {
printf("Error generating sha384 hash\n");
return 0;
}
printf("sha384_hash file is created: %s \n",sha384_hash);
return 1;
}
/**
* is_image_version_higher() iterates through each component and check
* versions against locally installed version.
@ -1151,6 +1183,75 @@ int split_code_signature_cert_from_component_bin_elf64(struct image_section *sec
return 1;
}
/**
* parse_elf_image_phdr() parses the ELF32 program header to get the
* ELF header of rootfs metadata. It parses the metadata and writes
* to a new /tmp/metadata.bin file.
*/
int parse_elf_image_phdr(struct image_section *section)
{
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
Elf32_Phdr *phdr; /* Program header structure pointer */
struct stat sb;
uint8_t *fp;
int i;
int fd = open(section->file, O_RDONLY);
if (fd < 0) {
perror(section->file);
return 0;
}
memset(&sb, 0, sizeof(struct stat));
if (fstat(fd, &sb) == -1) {
perror("fstat");
close(fd);
return 0;
}
fp = mmap(NULL, sb.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
if (fp == MAP_FAILED) {
perror("mmap");
close(fd);
return 0;
}
ehdr = (Elf32_Ehdr *)fp;
phdr = (Elf32_Phdr *)(((char*)fp) + ehdr->e_phoff);
printf(" ELF headers are initialized\n");
if (ehdr->e_type != ET_EXEC) {
printf("Not a valid elf image\n");
close(fd);
return 0;
}
/* Load each program header */
for (i = 0; i < NO_OF_PROGRAM_HDRS; ++i) {
if(phdr->p_type == PT_LOAD) {
printf(" PT_LOAD Segment Found\n");
printf("Parsing img_info load addr 0x%x offset 0x%x size 0x%x type 0x%x\n",
phdr->p_paddr, phdr->p_offset, phdr->p_filesz, phdr->p_type);
int size = sb.st_size - (phdr->p_offset + phdr->p_filesz );
if (size < 0x4000) {
printf("rootfs metada is not available\n");
return 1;
}
create_file("/tmp/metadata.bin", (char *)(fp + phdr->p_offset + phdr->p_filesz), size);
printf("rootfs meta data file: %s created with size:%x\n","/tmp/metadata.bin", size);
close(fd);
return 1;
}
++phdr;
}
close(fd);
return 1;
}
/**
* being used to calculate the image hash
*
@ -1502,6 +1603,16 @@ int sec_image_auth(void)
}
len = snprintf(buf, SIG_SIZE, "%s %s", sections[i].img_code, sections[i].file);
if (!strncmp(sections[i].type, "rootfs", strlen("rootfs"))) {
struct stat sb;
if (stat("/tmp/metadata.bin", &sb) == -1)
continue;
len = snprintf(buf, SIG_SIZE, "%s %s %s", sections[i].img_code,
"/tmp/metadata.bin", "/tmp/sha384_keyXXXXXX");
}
if (len < 0 || len > SIG_SIZE) {
perror("Array out of Index\n");
free(buf);

3
tools/sysupgrade.h
View file

@ -128,3 +128,6 @@ int is_image_authenticated(void);
int do_board_upgrade_check(char *);
int check_nand_preamble(uint8_t *);
int find_mtd_part_size(void);
int create_file(char *, char *, int );
int parse_elf_image_phdr(struct image_section *);
int compute_sha384(struct image_section *);